TPD4S009DCKRG4 - Quad 0.8pF 5.5V ESD Protection | TI
MPN: TPD4S009DCKRG4 ✓ Active| Qty | Unit Price | Extended |
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| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
TPD4S009DCKRG4 Overview
An ESD protection TVS (transient voltage suppressor) diode array is a type of circuit-protection semiconductor that clamps electrostatic-discharge and cable-discharge events before they reach sensitive transceiver silicon. Within the protection hierarchy, it sits alongside TVS diodes and surge protectors, serving as the first line of defense in power management and interface circuits.
Key features include an ultra-low 0.8 pF typical line capacitance, which preserves signal integrity on differential pairs running at multi-hundred-megabit rates; excellent channel-to-channel capacitance matching, which minimizes skew between the two legs of a differential pair; and a dedicated VCC pin that lowers clamping voltage during ESD strikes on powered systems. The device is rated for ±8 kV IEC 61000-4-2 contact discharge, the maximum Level 4 severity.
Architecturally, the four steering/clamping diodes route ESD current from any I/O line to the VCC rail and ground, so transient energy is shared across the array rather than concentrated at one junction. The low junction capacitance is achieved without sacrificing robust clamping, and the SC-70-6 footprint keeps parasitic inductance low — critical because even a few nanohenries of trace inductance raises the effective clamping voltage during a fast ESD edge.
Typical applications include HDMI, Display Port, and LVDS display-port ESD protection, USB and Ethernet differential-line protection, and ESD protection for high-speed digital interfaces in consumer, industrial, and networking equipment.
Design-wise, keep the device close to the connector and use short, direct traces to the protected lines; place a bulk capacitor near VCC to absorb diverted charge.
This page synthesizes distributor availability, drop-in alternatives, comparison tables, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for TPD4S009DCKRG4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
TPD4S009DCKR
✅ Drop-In📋 Reference alternative (not in catalog)
TPD4S010DCKR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
D1213A-04S-7
✅ Drop-In📋 Reference alternative (not in catalog)
TPD4S009DCKRG4 Specifications
| Configuration | 4-Channel ESD protection diode array |
| Working Voltage (VWM) | 5.5 V |
| Line Capacitance | 0.8 pF (typical) |
| ESD Rating (Contact) | ±8 kV (IEC 61000-4-2 Level 4) |
| Channels | 4 |
| VCC Pin | Yes (dedicated VCC pin for powered-system clamping) |
| Polarity | Unidirectional |
| Application | High-speed differential interfaces (HDMI, Display Port, LVDS) |
| Package | SC-70-6 / SOT-363 (DCK) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (G4 suffix denotes RoHS/green) |
| Lead Free | Yes (Pbfree code: Yes per web data) |
TPD4S009DCKRG4 Pin Configuration
| Pin 1 | I/O1 — Protected I/O line 1 (ESD clamp to VCC/GND) |
| Pin 2 | GND — Ground return for ESD current diversion |
| Pin 3 | I/O2 — Protected I/O line 2 (ESD clamp to VCC/GND) |
| Pin 4 | I/O3 — Protected I/O line 3 (ESD clamp to VCC/GND) |
| Pin 5 | VCC — Supply pin providing low-impedance diversion rail |
| Pin 6 | I/O4 — Protected I/O line 4 (ESD clamp to VCC/GND) |
Typical Applications
TPD4S009DCKRG4 is suitable for 6 applications: HDMI Port ESD Protection, Display Port / LVDS Interface Protection, USB Interface Protection, Industrial Fieldbus / RS-485 Node Protection, Ethernet Physical Layer Protection, Consumer Electronics Button/Connector I/O Protection.
HDMI Port ESD Protection
HDMI connectors are directly touched by users and cables, making them prime ESD entry points; the TPD4S009DCKRG4 is explicitly categorized by Mouser as a 4-channel Display/HDMI port ESD protection device. Its 0.8 pF typical capacitance and channel-to-channel matching preserve the TMDS differential pairs' skew and eye diagram, which would be destroyed by a conventional multi-pF TVS. Placed within a few millimeters of the connector pins with short direct traces to the DCK package, the array clamps ±8 kV IEC 61000-4-2 Level 4 contact strikes to the 5.5 V rail and ground. Because the HDMI TMDS pairs are capacitively sensitive, validate insertion loss at your maximum link rate after layout; the low 0.8 pF load keeps the compliance margin large even on multi-gigabit links.
Recommended
Display Port / LVDS Interface Protection
Display Port and LVDS links run fast differential signaling on externally accessible connectors, so they combine strict signal-integrity requirements with real ESD exposure. The TPD4S009DCKRG4's 0.8 pF line capacitance introduces minimal loading on each differential pair, and its excellent capacitance matching limits intra-pair skew that would otherwise convert to deterministic jitter. The dedicated VCC pin provides a low-impedance diversion path so strike energy is shared across the array rather than concentrated on one junction. Place one device adjacent to the connector with ground via stitching nearby; use a bulk capacitor on the VCC rail to absorb diverted charge. Verify that the 5.5 V working voltage exceeds the highest DC bias expected on the protected lines, including any AC-coupled common-mode offset.
Recommended
USB Interface Protection
USB connectors on consumer and industrial equipment face frequent hot-plug events and human contact, making ESD protection mandatory at the connector. The TPD4S009DCKRG4's four channels cover both D+/D- data lines plus CC/VBUS-adjacent signals in a single SC-70-6 package, saving board area versus discrete diodes. At 0.8 pF, the capacitance is well within USB 2.0 high-speed eye-diagram margins, and the ±8 kV IEC 61000-4-2 Level 4 contact rating absorbs strikes delivered through the receptacle shell to signal pins. Layout guidance: position the array between connector and transceiver, keep D+/D- traces length-matched through the device, and ground the array through multiple vias to the plane to minimize clamping voltage during fast ESD edges.
Recommended
Industrial Fieldbus / RS-485 Node Protection
Industrial installations expose cabling to handling, dust, and charged personnel, so ESD hardening at fieldbus connectors improves uptime. The TPD4S009DCKRG4 protects four lines - typically the A/B differential pair plus control or enable lines - at a single 5.5 V rail. Its ±8 kV IEC 61000-4-2 Level 4 contact rating meets the ESD severity commonly specified for industrial equipment interfaces, while the 0.8 pF capacitance keeps edge degradation negligible at typical RS-485 and CAN data rates. Combine with TVS surge protection and galvanic isolation in tiered protection schemes: the TPD4S009 handles fast low-energy ESD at the connector, while downstream surge devices handle high-energy transients. Confirm the bus common-mode voltage stays below the 5.5 V working rating under all fault conditions.
Recommended
Ethernet Physical Layer Protection
Ethernet magnetics present a low-capacitance requirement on line-side circuits, and external connectors remain an ESD path for exposed RJ45 or industrial M12 jacks. The TPD4S009DCKRG4's 0.8 pF capacitance minimizes insertion-loss penalty on 10/100BASE-T pairs, and channel matching avoids adding intra-pair skew that erodes return-loss margins. Four channels per package let one device protect two differential pairs, simplifying BOM consolidation. The ±8 kV IEC 61000-4-2 Level 4 rating absorbs strikes coupled through the magnetics or connector shell. Place the array on the system-side of the magnetics where lines are at 5.5 V or lower DC bias, and coordinate with downstream surge-rated devices for PoE or long-cable installations where higher-energy transients are expected.
Recommended
Consumer Electronics Button/Connector I/O Protection
Externally accessible buttons, card slots, and auxiliary connectors in consumer devices accumulate ESD exposure over the product lifetime. The TPD4S009DCKRG4 consolidates protection for four separate I/O lines into one SC-70-6 package occupying roughly 2 mm x 2.1 mm of board space, valuable in space-constrained mobile and wearable designs. Its 5.5 V working voltage covers 3.3 V and 5 V signaling domains, and the ±8 kV contact rating ensures survival of repeated user-contact strikes. The low capacitance is unimportant for slow GPIO but guarantees the part can also be reused on any clock or data line routed to the same connector. Standard lead-free reflow compatibility and tape-and-reel packaging support high-volume automated assembly without special handling.
Recommended
Recommended Products Summary
Engineering reference data for TPD4S009DCKRG4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | TPD4S009DCKR | TPD4S010DCKR | D1213A-04S-7 |
|---|---|---|---|---|
| Package | SC-70-6 (DCK / SOT-363) | SC-70-6 - same | SC-70-6 - same | SC-70-6 (SOT-363) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Diodes Incorporated |
| Channels | 4 | 4 | 4 | 4 |
| RoHS / Green | Yes (G4 suffix) | Yes | Yes | Yes |
| Pin-to-Pin Compatibility | reference | 100% (same die) | Same family pinout - verify voltage | Pin-compatible per substitution data - verify parameters |
Key Differentiators
- Identical-die G4 ordering option (vs TPD4S009DCKR)
- 5.5 V working voltage for 3.3 V/5 V rails (vs TPD4S010DCKR)
- Cross-brand second-source availability (vs D1213A-04S-7)
Design Notes
Place the TPD4S009DCKRG4 within a few millimeters of the connector being protected. ESD pulses have sub-nanosecond edges, so trace inductance of roughly 1 nH/mm raises the effective clamping voltage seen at the IC under protection - distance between the array and the connector directly degrades protection effectiveness. Route protected lines through the device with no stubs, and connect pin 2 (GND) directly to a low-impedance ground plane using multiple vias.
The dedicated VCC pin provides a low-impedance path that shares ESD current across the array's junctions. Place a bulk decoupling capacitor (per TI datasheet typical application values) close to the VCC pin so diverted charge has a local reservoir; without it, the ESD current can pump the VCC rail upward and stress downstream ICs. Confirm the protected lines' DC bias never exceeds the 5.5 V working voltage, including during hot-plug transients.
Do not substitute the larger-pin-count TPD4S009DGSR (VSSOP-10) or SOT-23-6 TPD4S009DBVR on a SC-70-6 footprint - they are different packages requiring PCB rework, though some comparison sites list them alongside the DCK parts. For signal integrity, verify insertion loss on the actual board at your maximum link rate; even 0.8 pF adds loss on very long traces. Estimated: at 5 Gbps, a 0.8 pF shunt adds roughly 0.5 dB insertion loss on a 50-ohm line - validate eye margins.
Compliance Information
RoHS Code: Yes and Pbfree Code: Yes per web comparison data; G4 suffix denotes TI green/RoHS-compliant ordering variant. REACH and conflict-minerals declarations available via TI environmental documents on ti.com.
