UCC5310MCDR - 4.3A Isolated Gate Driver, 3kVrms, SOIC-8 | Texas Instruments
MPN: UCC5310MCDR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.85 | $2.85 |
| 10 | $2.55 | $25.50 |
| 100 | $2.1 | $210.00 |
| 500 | $1.78 | $890.00 |
| 1,000 | $1.55 | $1,550.00 |
UCC5310MCDR Overview
An isolated gate driver is a device that provides both signal-level galvanic isolation and high-current buffering between a low-voltage PWM controller and the gate of a high-voltage power transistor. Within the broader system hierarchy, an isolated gate driver sits between the control logic (microcontroller, DSP, or PWM controller) and the power stage (MOSFET, IGBT, SiC, GaN), enabling safe control of high-voltage rails in motor drives, solar inverters, and industrial power supplies.
Key features of the UCC5310MCDR include 4.3 A peak source / 2.2 A peak sink output current, a Miller clamp transistor internal to the package that prevents unwanted parasitic turn-on of the driven FET during high dV/dt switching transients, an input-side undervoltage lockout (UVLO) at approximately 12 V referenced to the IGBT emitter, and up to 30 V VDD driver supply with 15 V VCC input range. The 3 kVrms isolation rating supports basic-grade functional isolation in industrial environments.
The device uses TI's capacitive-coupling isolation technology to transmit the PWM signal across the isolation barrier while rejecting common-mode transients typical of fast-switching power stages. The internal Miller clamp is rated to handle negative 5 V transients on the gate node, improving robustness in half-bridge configurations with long gate-drive loops.
Typical applications include IGBT/SiC MOSFET gate drive for solar string inverters, three-phase motor drive inverter stages, isolated DC-DC converter primary-side FET drive, industrial servo drives, and HEV/EV traction inverter auxiliary stages. The combination of integrated Miller clamp and 4.3 A drive strength is particularly valuable when driving large-module IGBTs or paralleled SiC MOSFETs where parasitic turn-on would otherwise cause shoot-through.
When designing with this device, place the driver physically close to the driven power transistor to minimize gate-loop inductance. Use a local bootstrap or isolated supply for VDD, and provide adequate PCB copper for thermal dissipation (the SOIC-8 package has moderate thermal resistance).
This page synthesizes distributor pricing, drop-in alternatives, comparison parameters, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for UCC5310MCDR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with UCC5310MCDR (same form factor and footprint) — differing in Package, Peak Sink Current.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
UCC5320MCDR
✅ Drop-In📋 Reference alternative (not in catalog)
UCC5350MCDR
✅ Drop-In📋 Reference alternative (not in catalog)
UCC5390MCDR
✅ Drop-In📋 Reference alternative (not in catalog)
UCC5310MCDWV
✅ Drop-In📋 Reference alternative (not in catalog)
SI8751AB-IS
✅ Drop-In✓ In Stock
$2.84 / Unit
View Datasheet →UCC5310MCDR Maximum Ratings & Electrical Characteristics
| Number of Channels | 1 |
| Peak Source Current | 4.3 A |
| Peak Sink Current | 2.2 A |
| Isolation Voltage (rms) | 3 kVrms |
| Input VCC Range | 3 V to 15 V |
| Driver VDD Range | Up to 30 V |
| UVLO Threshold | 12 V (with respect to IGBT emitter, M-variant) |
| Miller Clamp | Integrated |
| Operating Temperature | -40C to +125C |
| Package | SOIC-8 (D) |
| Pins | 8 |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
UCC5310MCDR Pin Configuration
| Pin 1 | VDD — Driver-side positive supply (up to 30 V) |
| Pin 2 | GND2 — Driver-side ground (referenced to power transistor emitter/source) |
| Pin 3 | OUT — Gate driver output to power transistor gate |
| Pin 4 | CLAMP — Miller clamp transistor output to power transistor gate |
| Pin 5 | VCCI — Input-side supply (3 V to 15 V) |
| Pin 6 | GND1 — Input-side ground |
| Pin 7 | IN+ — Non-inverting PWM input |
| Pin 8 | IN- — Inverting PWM input |
Typical Applications
UCC5310MCDR is suitable for 6 applications: Solar String Inverter IGBT/SiC Gate Drive, Three-Phase Motor Drive Inverter Stage, Isolated DC-DC Converter Primary FET Drive, Industrial Servo Drive Power Stage, HEV/EV Traction Inverter Auxiliary Gate Drive, Telecom Rectifier and Power Factor Correction.
Solar String Inverter IGBT/SiC Gate Drive
The UCC5310MCDR's 4.3 A source / 2.2 A sink drive strength, integrated Miller clamp, and 3 kVrms isolation are well-matched to driving IGBT or SiC MOSFET power stages in residential and commercial solar string inverters. The Miller clamp directly suppresses the dV/dt-induced parasitic turn-on that plagues half-bridge switching at 10-30 kHz, while the 3 kVrms isolation provides basic isolation coordination for grid-tied systems operating at 600-1500 V DC bus. Placed between the PWM controller and the power-switch module, it replaces discrete optocoupler-plus-driver designs with a single SOIC-8 IC, reducing BOM cost by roughly 30%.
Recommended
Three-Phase Motor Drive Inverter Stage
In industrial three-phase motor drives (servo, VFD, robotics), the UCC5310MCDR drives the six IGBTs or SiC MOSFETs in the inverter bridge at switching frequencies of 10-50 kHz. Its 4.3 A peak source current enables fast gate-charge transitions for large-module IGBTs rated up to 100 A, reducing switching losses by 15-20% compared to 2 A drivers. The integrated Miller clamp prevents shoot-through caused by the high dV/dt transitions of the 600-1200 V DC bus. Three UCC5310MCDR devices provide all six drive channels with minimal PCB area, simplifying layout versus discrete optocoupler solutions.
Recommended
Isolated DC-DC Converter Primary FET Drive
The UCC5310MCDR drives the primary-side MOSFET or SiC FET in full-bridge, half-bridge, or push-pull isolated DC-DC converters used in telecom, server, and industrial power systems. The capacitive isolation barrier rejects the high common-mode transients (up to 100 kV/us CMTI) generated by the switching power stage on the secondary side, while the 3 kVrms isolation rating is adequate for 1500 V bus systems. With 4.3 A source current, it drives primary FETs with Qg up to 100 nC at switching frequencies of 100-500 kHz, enabling high power density.
Recommended
Industrial Servo Drive Power Stage
Precision servo drives for CNC machinery, robotics, and industrial automation rely on the UCC5310MCDR to drive the inverter FETs at 20-100 kHz with sub-microsecond timing accuracy. The integrated Miller clamp and 4.3 A drive strength minimize dead-time requirements, allowing the inverter to operate closer to ideal switching conditions and improving servo loop bandwidth. The 3 kVrms basic isolation is appropriate for servo drives operating from 300-600 V DC bus rails, where functional isolation is sufficient and reinforced isolation is provided elsewhere in the system.
Recommended
HEV/EV Traction Inverter Auxiliary Gate Drive
In hybrid and electric vehicle powertrains, the UCC5310MCDR drives auxiliary SiC MOSFET stages such as onboard chargers, DC-DC converters, and air-conditioning compressors. Although the main traction inverter requires AEC-Q100 qualified reinforced-isolation drivers, the UCC5310MCDR's 3 kVrms basic isolation and 4.3 A drive strength are well-suited to auxiliary power stages where 400-800 V bus voltage is standard. The integrated Miller clamp prevents shoot-through in the high dV/dt environment typical of EV power electronics.
Recommended
Telecom Rectifier and Power Factor Correction
In telecom rectifier modules and PFC front-ends for server PSUs, the UCC5310MCDR drives the SiC MOSFET or IGBTs in totem-pole PFC or bridgeless PFC topologies at 50-200 kHz switching frequencies. The high dV/dt of GaN/SiC FETs makes the integrated Miller clamp especially valuable, as it prevents parasitic turn-on during the off-state. With 4.3 A source current, the UCC5310MCDR drives 100-150 V SiC FETs with Qg up to 30 nC efficiently, reducing conduction and switching losses in 3-10 kW rectifier modules.
Recommended
Recommended Products Summary
Engineering reference data for UCC5310MCDR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | UCC5320MCDR | UCC5350MCDR | UCC5390MCDR | UCC5310MCDWV | SI8751AB-IS |
|---|---|---|---|---|---|---|
| Package | SOIC-8 (D) | SOIC-8 (D) - same | SOIC-8 (D) - same | SOIC-8 (D) - same | SOIC-8 (DWV) - wide-body | SOIC-8 - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Silicon Labs |
| Isolation Voltage (rms) | 3 kVrms | 5 kVrms (reinforced) | 3 kVrms | 5 kVrms (reinforced) | 3 kVrms (wide-body package) | 5 kVrms (reinforced) |
| Miller Clamp | Integrated | Optional (M-suffix) | Integrated | Optional (M-suffix) | Integrated | No |
| Operating Temperature | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C |
Key Differentiators
- Integrated Miller clamp in compact SOIC-8 footprint (vs UCC5320SCDR (without Miller clamp))
- Lowest-cost 3 kVrms basic-isolation option in the UCC53x0 family (vs UCC5320MCDR (5 kVrms reinforced isolation))
- Higher drive strength than 2 A isolated gate drivers (vs UCC21530QDWKRQ1 (dual-channel, AEC-Q100))
Design Notes
Place the UCC5310MCDR physically within 25 mm of the driven power transistor gate pad to minimize gate-loop inductance. High gate-loop inductance causes ringing and overshoot during fast switching transitions, which can exceed the gate-oxide breakdown voltage of the driven MOSFET/IGBT/SiC FET. Use a wide (>=0.5 mm) gate-drive trace with adjacent ground return to maintain low impedance, and place the VDD bypass capacitor (>=1 uF ceramic) within 5 mm of the VDD pin (pin 1) per the UCC53x0 datasheet layout guidelines.
The driver-side VDD supply must be capable of sourcing the gate-charge current during switching transients. For driving a power transistor with 100 nC Qg at 100 kHz, the average VDD current is approximately 10 mA, but peak source current can reach 4.3 A. Use a low-ESR ceramic bypass capacitor (10 uF X7R) directly on VDD, plus a 0.1 uF high-frequency decoupling capacitor in parallel. Ensure VDD voltage stays above the UVLO threshold (12 V typical) under all load transients to prevent unintended gate drive shutdown.
The SOIC-8 (D) package has a thermal resistance of approximately 150 C/W junction-to-ambient, so continuous power dissipation above 0.5 W will cause the junction temperature to rise noticeably. For continuous high-frequency switching (e.g. >100 kHz with 100 nC Qg), dissipation is approximately 0.1 W at 1 A peak drive current and 30 V VDD - well within the SOIC-8 thermal budget. For higher-power applications, ensure adequate PCB copper thermal relief (>=100 mm^2 of 2-oz copper on the VDD pin pad) to keep junction temperature within safe limits.
Do not apply voltages above 30 V to the VDD pin, as this exceeds the absolute-maximum rating of the UCC5310MCDR per the UCC53x0 datasheet. Verify that the driven power transistor's gate-source voltage rating is not exceeded by the VDD supply - if VDD=15 V is used to drive a GaN FET with Vgs(max)=7 V, add a Zener diode clamp on the gate. Also note that the M-suffix variant uses 12 V UVLO referenced to the IGBT emitter (pin 2), not to GND2, so the emitter connection is critical for proper UVLO operation.
Compliance Information
RoHS and REACH compliant per TI product page. The UCC5310MCDR is not AEC-Q100 qualified; for automotive traction inverter or HEV/EV auxiliary drives, consider the AEC-Q100 qualified UCC21530QDWKRQ1.
