ADC/DAC
Produtos (2518)
LTC2321HUFD-16 - 16-Bit Dual SAR ADC, 2Msps, 28-QFN | ADI
The Analog Devices LTC2321HUFD-16 is a low-noise, high-speed dual 16-bit successive approximation register (SAR) analog-to-digital converter with differential inputs, wide input common-mode range, and an on-board temperature-compensated reference. Operating from a single 3.3V or 5V supply, the device delivers 2 Msps throughput per channel across two simultaneous sampling channels in a 28-pin QFN (4x5) package. What is a SAR ADC? A successive approximation register analog-to-digital converter is a type of ADC that performs a binary search through successive bit trials to digitize an analog input. SAR ADCs sit in the ADC hierarchy as: SAR ADC -> Nyquist-rate ADC -> data converter -> mixed-signal IC -> semiconductor. They are prized for excellent DC accuracy, low latency, deterministic latency, and very low power consumption relative to their throughput, which is why SAR ADCs dominate multi-channel precision data-acquisition front ends. Key features of the LTC2321HUFD-16 include a wide 8 V_P-P differential input range, ±4 LSB typical INL with no missing codes at 16 bits, 81 dB SNR, and a low-drift (20 ppm/°C max) on-board reference that is pin-selectable between 2.048 V and 4.096 V. The serial LVDS-compatible interface reduces digital noise coupling on the board while enabling fast data transfer to an FPGA or DSP. The H-grade version operates over the extended industrial temperature range and supports an automotive temperature grade, simplifying qualification for harsh-environment designs. Architecturally, the LTC2321HUFD-16 uses a capacitive charge-redistribution DAC for the SAR conversion and integrates the reference, reference buffer, and input drivers on-die. This reduces external BOM count and minimizes the analog front-end complexity. Each ADC channel has its own dedicated sampling network, allowing true simultaneous sampling at multi-phase, which is critical for phase-coherent measurements such as quadrature demodulation in software-defined radio. Typical applications include industrial process control and data acquisition, software-defined radio baseband I/Q digitization, motor control feedback loops, automotive sensor signal chains, medical instrumentation, and multichannel precision test equipment. The wide common-mode range makes it suitable for directly digitizing signals from bridge sensors, current shunts, and photodiode front-ends without additional level shifting. When designing with this device, route analog and digital grounds separately, place the bypass capacitors as close to the supply pins as possible, and treat the LVDS interface traces as a 100-ohm differential pair with controlled impedance. Always consult the ADI datasheet for the recommended layout and the reference decoupling network. This page synthesizes distributor pricing, drop-in alternative analysis, and practical design guidance not found in the manufacturer datasheet, providing an engineering-focused reference for selecting, sourcing, and implementing the LTC2321HUFD-16 in production designs.
LTC2321IUFD-12 - Dual 12-Bit+Sign 2Msps SAR ADC | Analog Devices
The Analog Devices LTC2321IUFD-12 is a low-noise, high-speed dual 12-bit + sign successive approximation register (SAR) analog-to-digital converter with differential inputs and a wide input common-mode range, packaged in a 28-lead 4x5 mm QFN (UFD). Operating from a single 3.3V or 5V supply, the device delivers 2 Msps per channel with zero cycle latency, making it well suited for simultaneous-sampling multi-channel signal chains. An SAR ADC is a successive approximation register analog-to-digital converter that performs a binary search through an internal DAC to digitize an analog input in N conversion cycles. SAR converters occupy the middle ground between slow but precise delta-sigma ADCs and very fast but pipeline-limited flash ADCs, combining low latency, deterministic throughput, and excellent DC accuracy. Within the broader signal-chain taxonomy, the LTC2321IUFD-12 sits under: ADC -> data converter -> mixed-signal IC -> semiconductor. It is part of Analog Devices' LTC2321 family, which shares a common 28-QFN (4x5) footprint across 12-bit, 14-bit, and 16-bit resolutions. Key specifications include an 8V peak-to-peak differential input range, 73 dB SNR, ±0.5 LSB INL (typical), no missing codes at 12 bits, and an onboard 20 ppm/°C max low-drift 2.048V or 4.096V temperature-compensated reference. The high-speed SPI-compatible serial interface supports both single-ended CMOS and LVDS modes, giving the part flexible data-link options for FPGA, DSP, and MCU hosts. The wide common-mode range simplifies front-end signal conditioning and supports high-CMRR designs. Typical applications include motor control and phase-current sensing, multi-axis position encoders, simultaneous-sampling data-acquisition front-ends, and high-speed instrumentation. Its dual-channel architecture with matched sampling eliminates inter-channel skew for control loops that require phase-accurate measurements. When designing with the LTC2321IUFD-12, choose the 3.3V or 5V supply carefully to match the LVDS or CMOS I/O domain of the host. Decouple the AVDD and REFCAP pins locally with low-ESR ceramic capacitors, and route the analog and digital grounds using a star-ground or split-plane technique to minimize coupling of digital switching noise into the analog front end. This page synthesizes distributor pricing, drop-in alternatives drawn from the same 28-QFN family, and practical design notes not found in the manufacturer datasheet, giving engineers a one-stop engineering reference for the LTC2321IUFD-12.
LTC2321IUFD-14 - 14-Bit+Sign Dual 2Msps SAR ADC | ADI
The Analog Devices LTC2321IUFD-14 is a low-noise, high-speed dual 14-bit + sign successive approximation register (SAR) analog-to-digital converter with differential inputs and wide input common-mode range. Operating from a single 3.3V or 5V supply, the part achieves ±1LSB INL over an 8VP-P differential input range and supports throughput rates up to 2Msps per channel, packaged in a 28-pin QFN (4x5) with exposed pad. An SAR ADC is a successive-approximation converter that uses a binary-search algorithm against an internal DAC to digitize an input voltage in N conversion cycles for an N-bit code. SAR ADCs sit in the data-converter hierarchy below pipelined and delta-sigma ADCs but offer deterministic latency, low latency per conversion, and low power consumption - well suited for multiplexed multi-channel systems where each channel must be sampled at known, fixed time intervals. Key features include ±1LSB INL (max), 73dB SNR at 1Msps, an internal 20ppm/°C reference, and a serial SPI/LVDS digital interface with echo clock. The differential inputs provide wide common-mode rejection, making the device robust in noisy industrial environments where ground bounce is present. The 28-QFN (4x5) exposed pad reduces thermal resistance to about 28°C/W, allowing sustained 2Msps operation without external heatsinking. Internally, the LTC2321-14 uses two matched sample-and-hold amplifiers feeding independent SAR cores that share a single bandgap reference. Digital I/O supports both standard SPI and low-voltage differential signaling (LVDS) for noise-immune clock and data lines when paired with an FPGA. Internal dithering techniques flatten the noise floor and improve spurious-free dynamic range. Typical applications include multichannel data acquisition systems, motor control current sensing, biomedical instrumentation, and industrial process control. The wide 8VP-P input range lets the LTC2321IUFD-14 directly digitize +/-10V-referred signals after a simple resistor-divider scaling stage, eliminating an instrumentation-front-end in many designs. When designing with this ADC, keep analog input traces short and matched, decouple VDD with a 10µF ceramic + 1µF X7R pair, and tie the exposed pad to a clean analog ground plane. Note that the LTC2321IUFD-14 is graded for the -40°C to +85°C industrial range; choose LTC2321HUFD-14 for the -40°C to +125°C automotive grade. This page synthesizes distributor pricing, drop-in and pin-compatible alternatives, and practical design guidance beyond what the manufacturer datasheet alone provides - useful when the LTC2321IUFD-14 is approaching obsolescence and you need a sourcing or replacement plan.
LTC2323HUFD-16 - Dual 16-Bit 5Msps SAR ADC | Analog Devices
The Analog Devices LTC2323HUFD-16 is a low-noise, high-speed dual 16-bit successive approximation register (SAR) analog-to-digital converter with differential inputs and a wide input common-mode range. Operating from a single 3.3V or 5V supply, the LTC2323HUFD-16 supports an 8V_P-P differential input range and achieves ±4LSB INL maximum with 5Msps per channel throughput. The H-grade device is specified over the -40C to +125C automotive/industrial temperature range and is housed in a 28-lead 4mm x 5mm QFN package with exposed pad. An ADC (analog-to-digital converter) is an integrated circuit that samples a continuous analog voltage and converts it into a discrete digital code. SAR (successive-approximation-register) ADCs use a binary-search algorithm with an internal DAC and comparator to resolve N bits in N clock cycles, trading speed for very low power and deterministic latency. Within the broader taxonomy, the LTC2323-16 belongs to the high-speed precision SAR converter family, itself a subset of data-converter ICs, which sit inside the signal-conditioning block of mixed-signal acquisition systems. Differential-input SAR ADCs like this one reject common-mode noise picked up on long sensor or transmission-line runs. Key features include an onboard low-drift (20 ppm/C maximum) 2.048V or 4.096V temperature-compensated reference, a high-speed SPI-compatible serial interface that supports both CMOS and LVDS modes, and one-cycle latency that simplifies software timing. The wide 8V_P-P differential input range enables high-dynamic-range acquisition with high common-mode rejection, while the internal reference eliminates external reference cost and board area. CMOS or LVDS digital I/O lets the designer trade noise immunity against the number of PCB traces. The architecture combines two matched SAR cores with shared reference and clock generation, allowing simultaneous sampling on both channels without inter-channel skew penalties. The 5Msps per channel rate and one-cycle latency make the part well-suited to multiplexed data-acquisition front-ends, motor-control feedback loops, and multi-axis vibration or sonar arrays where deterministic timing matters. Typical applications include industrial process control and instrumentation, multi-axis motor control, medical imaging front-ends, and automotive sensor acquisition. Differential inputs pair naturally with bridge sensors, current-sense shunts, and active drive signals where common-mode voltage can swing across the supply rails. When designing with this part, place input RC anti-alias networks close to the analog pins and route LVDS pairs with 100-ohm differential impedance. Use the exposed pad as the primary thermal path; an unbroken top-layer ground plane directly under the EP is recommended for full-speed operation across temperature. This page synthesizes distributor pricing, drop-in package-matched alternatives, and practical PCB-layout notes not found in the manufacturer datasheet, giving engineers a single decision-ready reference for selecting and sourcing the LTC2323HUFD-16.
LTC2335CLX-16 - 16-Bit 1Msps 8-Ch SAR ADC | Analog Devices
The Analog Devices LTC2335CLX-16#PBF is a 16-bit, 1 Msps, 8-channel multiplexed successive approximation register (SAR) analog-to-digital converter with differential inputs and a wide common-mode range, supplied in a 48-pin LQFP (7 mm x 7 mm) package. According to the Analog Devices LTC2335-16 datasheet, the device provides SoftSpan configurable true bipolar input ranges of +/-10.24 V, 0 V to 10.24 V, +/-5.12 V, or 0 V to 5.12 V on a per-conversion basis, driven by an internal 2.048 V reference and an internal reference buffer. The LTC2335CLX-16 is the commercial-temperature grade (0 C to +70 C) of the LTC2335-16 family and operates from a single 5 V low-voltage analog supply plus flexible high-voltage input supplies. An SAR ADC is a successive-approximation-register analog-to-digital converter, a class of precision converter that uses an iterative binary-search algorithm against an internal DAC to resolve one conversion in N cycles for an N-bit result. Within the broader ADC taxonomy, the LTC2335CLX-16 sits in the precision low-noise multichannel SAR ADC sub-category, itself a member of the data-converter family and signal-chain semiconductor hierarchy used in industrial, instrumentation, and test-and-measurement equipment. Key specifications include 16-bit resolution with no missing codes, 1 Msps throughput on a single channel, eight analog input channels with software-selectable channel sequencing, an 8.192 V p-p differential input range on its highest span, and integrated reference and reference buffer. The wide common-mode input range simplifies direct connection to bridges, thermocouples, and current-sense amplifiers without external level shifters. The converter architecture combines a capacitive charge-redistribution DAC, an internal low-drift reference, and an input analog front end that supports true bipolar signals in software rather than via external front-end circuitry, reducing BOM area. Typical integral non-linearity is approximately 1 LSB with excellent AC performance at lower output rates. Typical applications include multi-channel industrial process control, multiplexed data-acquisition front ends, instrumentation and test equipment, optical-module monitoring, and power-supply supervisory boards. The combination of 1 Msps speed and 8-channel input multiplexer makes it a strong fit for any application that scans multiple sensors or rails in a single chip. When designing with the LTC2335CLX-16, ensure adequate decoupling on both the 5 V analog and high-voltage input supplies and keep the analog ground return paths short and direct. For noise-critical designs, average multiple conversions to further reduce effective input-referred noise. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not consolidated in the manufacturer datasheet alone.
LTC2335HLX-16 - 16-Bit, 1Msps 8-Ch SAR ADC | Analog Devices
The Analog Devices LTC2335HLX-16 is a 16-bit, low-noise, 8-channel multiplexed successive approximation register (SAR) analog-to-digital converter with differential, wide common-mode range inputs, sampling at 1 Msps, and housed in a 48-pin LQFP (7x7) package. The device operates from a 5 V low-voltage supply and flexible high-voltage supplies while using an internal reference, providing differential input ranges of ±10.24 V with ±1 LSB INL and no missing codes at 16-bit resolution. What is a SAR ADC? A successive approximation register analog-to-digital converter is a precision ADC architecture that uses a binary search algorithm to convert an analog input to a digital code over N clock cycles. SAR ADCs sit within the hierarchy of ADC types as the mid-speed, mid-resolution choice — faster than delta-sigma but lower power than pipelined — and they are favored for multiplexed multi-channel data acquisition because they settle quickly between conversions. Key features of the LTC2335HLX-16 include 94.4 dB SNR, ±1 LSB INL guaranteed, no missing codes at 16 bits, an internal precision reference, wide common-mode input range, and flexible SoftSpan input ranges configurable per channel. The integrated 8-to-1 analog input multiplexer with channel-by-channel range selection makes it ideal for systems requiring dynamic range across multiple sensor or signal inputs. From an architectural perspective, the LTC2335-16 family uses a charge-redistribution DAC array driven by a SAR engine, achieving 16-bit deterministic latency. The wide common-mode input range simplifies front-end signal conditioning when digitizing differential signals riding on high-voltage rails — a common requirement in industrial control, power-line monitoring, and instrumentation front ends. Typical applications include multichannel data acquisition systems, programmable logic controllers, industrial process control, power-line monitoring, and instrumentation requiring wide dynamic range across multiple input channels. The 1 Msps throughput combined with eight input channels makes it attractive for simultaneous-sampling-adjacent designs and time-multiplexed high-voltage measurement systems. When designing with this device, place the bypass capacitors directly adjacent to the analog and reference supply pins. Decouple the OVDD logic supply separately from the analog supplies, and respect the absolute maximum ratings on analog inputs to avoid latch-up. This page consolidates distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, with all data cross-referenced against the LTC2335-16 datasheet.
LTC2335HLX-18 - 18-Bit 1Msps 8-Ch SAR ADC | Analog Devices
The Analog Devices LTC2335HLX-18 is an 18-bit, 1 Msps, 8-channel multiplexed successive approximation register (SAR) analog-to-digital converter with differential inputs and a wide common-mode range, housed in a 48-pin LQFP (7x7 mm) package. It accepts input ranges of ±10.24 V, 0 V to 10.24 V, ±5.12 V, or 0 V to 5.12 V on a per-conversion basis via the SoftSpan interface, and delivers ±3 LSB INL, no missing codes at 18-bit resolution, and 96.7 dB SNR. The 'H' speed grade in this order code designates the 1 Msps sampling rate. A SAR ADC is a successive approximation register analog-to-digital converter that performs a binary search against the analog input using an internal DAC. Each conversion takes N clock cycles for an N-bit result, making SAR ADCs well-suited to multiplexed multi-channel systems because they offer low latency, deterministic throughput, and zero pipeline delay. The LTC2335HLX-18 sits within the data-converter hierarchy as: SAR ADC -> ADC -> data converter -> signal chain IC -> semiconductor. Key features include 8 software-selectable input channels, pin-selectable SPI CMOS (1.8 V to 5 V) and LVDS serial interfaces, an internal 2.048 V or 4.096 V reference with buffer, 118 dB CMRR, and a 5 V analog supply plus flexible high-voltage analog supplies for the input stage. These features allow a single ADC to digitize multiple sensor rails without external signal conditioning. The architecture combines an 8-to-1 analog input mux, a charge-redistribution 18-bit CDAC, an internal low-drift reference, and an LVDS/CMOS digital engine. Pin-configurable SoftSpan input ranges let the same ADC handle true bipolar ±10 V signals alongside unipolar 0-5 V signals, eliminating external ranging amplifiers in most PLC, ATE, and industrial data-acquisition boards. Typical applications include industrial process control and PLC analog modules, automated test equipment (ATE) and instrumentation, multi-channel data acquisition systems, medical imaging front ends, and high-end vibration or seismic monitoring where wide dynamic range and high channel density are required. When designing with this device, ensure the analog and digital grounds are tied at a single point near the ADC, place the 10 µF bypass capacitor close to the REFIN pin, and use controlled-impedance routing for the LVDS lines if the LVDS interface is selected. The LVDS mode supports higher throughput at long trace lengths, while CMOS mode simplifies low-channel-count designs. This page synthesizes distributor pricing, 48-pin LQFP drop-in alternatives, design notes, and AEO-optimized comparison data not consolidated on the manufacturer datasheet, helping engineers accelerate multi-channel precision data-acquisition design and second-source decisions.
LTC2335ILX-16 - 16-Bit 1Msps 8-CH SAR ADC | Analog Devices
The Analog Devices LTC2335ILX-16 is a 16-bit, 1 Msps, 8-channel differential successive approximation register (SAR) analog-to-digital converter with wide common-mode input range, integrated precision reference and reference buffer, housed in a 48-lead LQFP (7x7 mm) package. The SoftSpan architecture accepts ±10.24 V, 0 V to 10.24 V, ±5.12 V, or 0 V to 5.12 V true bipolar or unipolar input spans on a conversion-by-conversion basis. Operating from a single 5 V low-voltage supply with flexible high-voltage supplies, the device achieves 16-bit no-missing-codes performance and is specified over the industrial -40 °C to +85 °C temperature range. A SAR ADC is a successive approximation register analog-to-digital converter, a converter architecture that uses a binary-search algorithm against an internal DAC to resolve each sample in N clock cycles. SAR ADCs sit in the broader hierarchy: ADC -> data converter -> mixed-signal IC -> signal chain IC. The LTC2335ILX-16 family specifically belongs to the multiplexed, high-impedance, wide-common-mode SoftSpan SAR ADC class designed for multi-channel data acquisition systems. Key features include 16-bit resolution with no missing codes, 1 Msps throughput, 8 differential input channels with hardware or sequencer channel selection, per-channel input span switching via SoftSpan, integrated low-drift 2.048 V reference, integrated reference buffer, and a high-speed SPI-compatible serial interface. Internal channel-specific digital averaging modes reduce noise at the expense of throughput. Differential inputs support ±10.24 V true bipolar signals without external front-end signal conditioning. The analog input structure uses charge-balancing switched-capacitor front ends per channel with shared reference and buffer, simplifying PCB layout when measuring multi-channel high-voltage signals. The internal reference and buffer eliminate external components for unipolar and bipolar spans. The SoftSpan interface reconfigures the input range on every conversion, allowing heterogeneous signal conditioning across channels at full 1 Msps aggregate throughput. Typical applications include multi-channel industrial process control and data acquisition, programmable logic controller (PLC) analog input modules, automated test equipment (ATE) and instrumentation, power-line and motor-control voltage monitoring, and any multi-channel precision measurement requiring mixed bipolar and unipolar signal ranges. Designers favor this ADC when 8 differential channels, ±10 V true bipolar operation, and integrated reference reduce BOM and PCB area. Design consideration: ensure the HV supply rail is sized for the largest programmed span; the 5 V low-voltage supply must be a low-noise LDO or ferrite-filtered switching regulator output. PCB layout should keep analog inputs short, symmetric, and routed over a continuous ground plane under the analog side of the IC. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, enabling faster component selection for multi-channel precision data-acquisition designs.
LTC2335ILX-16#PBF - 16-Bit 1Msps 8-CH SAR ADC | Analog Devices
The Analog Devices LTC2335ILX-16#PBF is a 16-bit, 1 Msps, 8-channel multiplexed successive approximation register (SAR) analog-to-digital converter with differential, wide common-mode range inputs, housed in a 48-pin LQFP (7x7 mm) package. It accepts input spans configurable through Analog Devices' SoftSpan feature up to ±10.24 V, supports input common-mode voltages far beyond the supply rails, and runs from a single 5 V low-voltage supply plus flexible high-voltage analog rails. The internal 2.048 V reference and integrated reference buffer simplify board design by eliminating the need for external precision references in most applications. SAR ADCs like the LTC2335-16 sit in the converter hierarchy as successive-approximation register converters within the broader analog-to-digital converter family, ultimately part of the data-acquisition and signal-chain integrated circuit category. They are widely chosen over flash or pipeline ADCs when designers need a precise, low-latency, deterministic sampling of multi-channel analog signals at moderate-to-high sample rates without the latency or complexity of pipelined architectures. Key features of the LTC2335ILX-16#PBF include 16-bit resolution with no missing codes, 1 Msps throughput on a single channel (or 125 kps aggregate when cycling all eight channels), a wide ±10.24 V true bipolar input range through SoftSpan, 90 dB CMRR at 100 kHz, low 1.3 mA supply current at 1 Msps, and an SPI-compatible serial interface for microcontroller or FPGA data retrieval. The internal reference and buffer trim board complexity to a handful of decoupling capacitors and a single programming word per conversion. Architecturally, the LTC2335-16 pairs a charge-redistribution CDAC with a low-noise comparator and on-chip conversion clock, while an integrated input multiplexer and wide-common-mode front end allow each channel to digitize signals far above or below ground regardless of the supply rail. The SoftSpan configuration lets the designer trade full-scale range against noise for each channel without external resistor networks. Typical applications include industrial process control and multi-channel PLC analog front ends, high-speed multi-axis data acquisition systems, programmable logic controller (PLC) inputs, optical networking monitoring, and medical instrumentation such as patient monitoring front ends. Its bipolar ±10.24 V input range maps directly to industrial ±10 V transducer outputs without external scaling. When using the LTC2335ILX-16#PBF, design the layout to keep the analog and digital grounds separated by a single-point star and provide a low-impedance 5 V AVCC with 1 µF + 0.1 µF decoupling close to the supply pins. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that complement the manufacturer datasheet rather than duplicating it.
LTC2341HUH-16 - Dual 16-Bit 666ksps SAR ADC | Analog Devices
The Analog Devices LTC2341HUH-16 is a 16-bit, low-noise dual-channel simultaneous-sampling successive approximation register (SAR) analog-to-digital converter with differential, wide common-mode-range inputs. Each channel can be independently configured on a conversion-by-conversion basis for soft-span ranges of ±4.096V, 0V to 4.096V, ±2.048V, or 0V to 4.096V. The device operates from a 5V supply, supports an external reference, and integrates an internal reference and buffer; throughput is 666 ksps per channel. It is housed in a 32-pin QFN (5x5 mm) package. According to the Analog Devices LTC2341-16 datasheet, the part supports pin-selectable SPI CMOS (1.8V to 5V) and LVDS serial interfaces, with one or two lanes of CMOS data output selectable to optimize bus width and throughput. A SAR ADC is a type of analog-to-digital converter that uses a successive approximation register and an internal DAC to converge on the input voltage one bit per clock cycle. Compared to delta-sigma ADCs, SAR converters deliver deterministic latency, single-cycle conversions, and excellent DC accuracy, making them well suited to multiplexed data-acquisition systems, control loops, and instrumentation. The dual simultaneous-sampling architecture lets the LTC2341HUH-16 capture two channels with channel-to-channel skew of only a few nanoseconds. Key features include 16-bit resolution with no missing codes, 86.5 dB SNR (typical at ±4.096V range), pin-selectable SPI CMOS or LVDS interfaces, an internal 4.096V reference with integrated buffer, and per-channel soft-span input ranges. The device supports an external reference option for designs that need ratiometric measurements or non-standard full scales. Technically, the SAR core is built on a switched-capacitor charge-redistribution architecture with an integrated front-end multiplexer; the analog inputs are truly differential and the wide common-mode range allows direct connection to bipolar signals, single-ended rails, and ground-referenced transducers without external level shifting. Built-in reference decoupling and an internal buffer minimize external component count and reduce PCB footprint. Typical applications include multichannel data-acquisition systems, industrial process control, instrumentation, automatic test equipment (ATE), and any design that requires simultaneous sampling of two analog signals with deterministic latency. The part is also a strong fit for multi-axis motor control and vibration analysis, where phase coherence between channels is critical. When designing with the LTC2341HUH-16, ensure clean analog and digital ground separation and place the 10uF reference bypass capacitor as close to the REFIN pin as possible. Use controlled-impedance routing for LVDS lines when the LVDS interface is selected at high throughput, and verify the digital I/O logic-level compatibility (CMOS mode supports 1.8V to 5V VIO). This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, with all specifications cross-referenced against the Analog Devices LTC2341-16 datasheet (234116f).
LTC2341HUH-18 - 18-Bit, 666kSPS Dual SAR ADC | ADI
The Analog Devices LTC2341HUH-18 is a dual-channel, 18-bit, 666 ksps/ch simultaneous-sampling successive approximation register (SAR) analog-to-digital converter (ADC) in a 32-lead 5mm x 5mm QFN (QFN-32 with exposed thermal pad) package. Each channel delivers true 18-bit resolution with differential wide-common-mode inputs, pin-selectable SPI CMOS (1.8 V to 5 V) and LVDS serial interfaces, and integrated 2.5 V reference with buffer. The part supports SoftSpan input ranges spanning ±10.24 V and 0 V to 10.24 V on each channel independently, supplied from a single 5 V analog rail. A SAR ADC is a successive-approximation-register analog-to-digital converter that uses a binary-search algorithm against a precision reference to resolve each input sample in N bit-clock periods. The SAR family sits in the broader hierarchy: ADC -> data converter -> mixed-signal IC -> signal chain. Within ADC families, SAR converters bridge the gap between the speed of pipeline ADCs and the noise precision of sigma-delta ADCs, making them the topology of choice for multiplexed or simultaneous multi-channel data acquisition (DAQ) systems where zero latency and true bipolar input range are required. Key features of the LTC2341HUH-18 include a maximum conversion rate of 666 ksps per channel, integrated 2.5 V low-drift reference, on-chip reference buffer, simultaneous sampling across both channels, wide input common-mode range, pin-selectable CMOS/LVDDS digital interface (1.8 V to 5 V logic), and 32-QFN (5x5) thermally-enhanced packaging. The SoftSpan feature allows per-channel input range reconfiguration without external scaling resistors, drastically simplifying front-end design for multi-range DAQ systems. From an architectural perspective, the LTC2341HUH-18 uses a charge-redistribution SAR core with proprietary common-mode sampling, enabling true differential input sampling over a ±10.24 V common mode. The integrated reference and buffer eliminate the need for an external low-noise reference plus dedicated reference buffer, reducing BOM count and PCB area. The CMOS or LVDDS serial interface is pin-selectable, allowing the same device to communicate with legacy 5 V microcontrollers, modern 1.8 V FPGAs, or LVDS-class ASICs. Typical applications include industrial process control and instrumentation, automatic test equipment (ATE), programmable logic controllers (PLC) analog input modules, multi-channel data acquisition (DAQ) boards, and precision medical instrumentation. The simultaneous-sampling capability is especially valuable in polyphase power, sonar, and vibration analysis where inter-channel phase coherence must be preserved. When designing with the LTC2341HUH-18, use solid ground planes, place the 10 uF decoupling capacitor immediately at AVDD/DVDD, route differential inputs as tightly-coupled pairs, and follow the recommended layout in the manufacturer datasheet to achieve datasheet SNR/THD performance. Avoid sharing the analog ground return with noisy digital return currents; star-ground the exposed pad to a quiet AGND pour. This page synthesizes verified distributor pricing, drop-in alternative cross-references, and practical design guidance for the LTC2341HUH-18 that go beyond the manufacturer datasheet - including same-family variants and cross-brand equivalents sharing the same 32-QFN (5x5) footprint.
LTC2341IUH-16 - 16-Bit Dual 666ksps SAR ADC | Analog Devices
The Analog Devices LTC2341IUH-16 is a 16-bit, low-noise, dual-channel simultaneous-sampling successive approximation register (SAR) analog-to-digital converter with differential, wide common-mode-range inputs. Housed in a 32-pin QFN (5x5 mm, UH suffix) package, it samples two channels at 666 ksps each (1.332 Msps aggregate) while operating from a single 5V supply. A SAR ADC is a successive approximation register analog-to-digital converter. It performs one bit at a time using an internal binary search through a precision DAC, achieving high accuracy and deterministic latency per conversion. SAR ADCs sit within the broader data-converter hierarchy as part of the ADC class, alongside delta-sigma, pipeline, and flash converters. They are widely chosen for multiplexed data acquisition, control loops, and instrumentation where moderate resolution (12-18 bits) is paired with multi-MHz sampling and no latency penalty. The LTC2341-16 family extends this architecture with simultaneous sampling, per-channel span control, and bipolar true-differential inputs. Key features include pin-selectable SPI CMOS (1.8V to 5V) and LVDS serial interfaces, support for one or two output lanes in CMOS mode for bus-width optimization, and Analog Devices' SoftSpan technology enabling each channel's input range to be set on a per-conversion basis across eight software-selectable spans from ±10.24V down to 0V to 5.12V. The internal 2.048V reference and buffer, 93.5dB SNR (typical), and 90dB common-mode rejection generate performance suitable for precision data acquisition. Architecturally, the LTC2341-16 uses a charge redistribution SAR core with simultaneous track-and-hold on both channels, eliminating inter-channel skew that would otherwise corrupt two-channel phase measurements. The wide common-mode range lets each input tolerate large DC offsets independent of the differential signal amplitude, simplifying front-end signal conditioning when interfacing with industrial sensors, bridge transducers, or PLC outputs. Typical applications include industrial process control and PLC analog input modules, multi-channel data acquisition systems, ATE-friendly test and measurement instrumentation, medical imaging front ends, and any multi-channel precision instrumentation requiring simultaneous sampling. The wide input range also supports direct connection to ±10V industrial signals without external attenuation. When designing with this device, provide clean low-impedance analog inputs and decouple the 5V supply close to the AVdd pins with a 10uF ceramic plus 0.1uF bypass network. The internal reference eliminates external reference cost while still delivering 16-bit linearity, but layout must keep digital return currents away from sensitive analog ground to preserve the 93.5dB SNR figure. This page synthesizes distributor pricing, drop-in compatible same-package alternatives (LTC2341IUH-18, LTC2249IUH), cross-reference guidance, and practical design notes not found in the manufacturer datasheet alone.
LTC2344CUH-16 - Quad 16-Bit 400ksps/ch SoftSpan SAR ADC | Analog Devices
The Analog Devices LTC2344CUH-16 is a quad, 16-bit, 400 ksps per channel, simultaneous-sampling successive approximation register (SAR) analog-to-digital converter with differential, wide common-mode-range inputs, housed in a 32-pin QFN (5x5) package. Each channel features a flexible SoftSpan input range from ±10.24V down to 0V to 5.12V set on a per-conversion basis, ±1.25 LSB INL, 93.4 dB SNR, 102 dB CMRR, and guaranteed no-missing-codes at 16-bit resolution. The device operates from a single 5V analog supply and a 1.8V to 5V digital supply, supporting both SPI CMOS and LVDS serial interfaces selectable per lane. What is a SAR ADC? A successive-approximation-register analog-to-digital converter is a precision data converter that performs a binary search through an internal capacitive network, comparing the sampled input against an internal DAC one bit per clock cycle to converge on the digital output. SAR ADCs sit in the broader ADC family alongside delta-sigma, pipeline, and flash converters; they offer an excellent balance of resolution (16-20 bits), sampling rate (100 ksps to multi-MB ms), latency (single-cycle, deterministic), and power consumption, which is why they dominate multiplexed data-acquisition, industrial instrumentation, and high-speed control-loop applications. Key features include per-channel independent input ranges, true simultaneous sampling across all four ADCs, an integrated precision reference and reference buffer, pin-selectable SPI/LVDS interface, and configurable one-to-four-lane CMOS output for bus-width optimization. The combination of 93.4 dB SNR and 102 dB CMRR allows the part to directly digitize wide common-mode signals in noisy industrial environments without front-end signal conditioning. Typical applications include industrial process control and multichannel data acquisition systems, medical instrumentation such as patient monitoring and ECG/EMG front ends, optical networking, and multi-axis motor control. The simultaneous-sampling architecture is particularly valuable in three-phase power monitoring and vibration analysis where channel-to-channel phase relationships must be preserved. When designing with this device, place the internal reference bypass capacitor and decoupling capacitors close to the pins and follow the Analog Devices reference layout for the exposed pad. The SoftSpan per-channel range control requires writing the range register between conversions, which must be accounted for in software timing. Pricing and availability data are quoted as of 2026-10-13. This page synthesizes distributor stock, drop-in same-package alternatives, and design considerations not collected in the manufacturer datasheet alone.
LTC2344CUH-18 - 18-Bit 400kSPS Quad SAR ADC | Analog Devices
The Analog Devices LTC2344CUH-18 is an 18-bit, 400 kSPS per channel, simultaneous-sampling 4-channel SAR analog-to-digital converter with differential, wide common-mode-range SoftSpan front ends, packaged in a 32-pin QFN (5x5 mm) with exposed pad. Operating from a single 5 V supply, the device integrates a precision internal reference and buffer, plus a per-channel sample-and-hold, enabling true simultaneous acquisition across four channels without inter-channel latency. A successive approximation register (SAR) ADC is a precision data converter architecture that resolves one bit per clock cycle using a binary-weighted capacitor DAC and a comparator, then digitizes the input through a successive approximation search. SAR ADCs are valued for low latency, deterministic behavior, no pipeline latency, and excellent DC accuracy. Within the converter family hierarchy, SAR ADCs sit below pipelined ADCs (higher speed, higher channel count) and delta-sigma ADCs (highest resolution, lowest bandwidth); the LTC2344 family targets the mid-bandwidth, multi-channel, high-precision industrial segment. Key specifications include 18-bit resolution with no missing codes, 400 kSPS per channel simultaneous sampling rate, four differential SoftSpan inputs accepting true bipolar ±10.24 V or 0-5 V ranges, 100 dB SNR typical, and ±2 LSB INL maximum. The serial interface supports pin-selectable SPI CMOS (1.8 V to 5 V) or LVDS output, with one to four lanes selectable in CMOS mode to optimize bus width and throughput. The internal 2.048 V reference and buffer reduce external component count. Typical applications include industrial process control and automation, multi-channel data acquisition systems, medical imaging front ends, instrumentation and test equipment, and high-speed multichannel precision monitoring. The 32-QFN package with exposed pad provides low thermal resistance suitable for continuous high-throughput conversion. When designing, decouple AVDD/DVDD/OVDD with 1 µF and 0.1 µF ceramic capacitors placed as close to the pins as possible. Drive the CNV rising edge to start conversion; route the LVDS or CMOS data lines with controlled impedance and length-matching. The exposed pad must be soldered to a continuous ground plane for thermal dissipation and low-impedance return paths. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone manufacturer datasheet.
LTC2344HUH-16 - 16-Bit 4-Ch 400ksps SoftSpan SAR ADC | ADI
The Analog Devices LTC2344HUH-16 is a 16-bit, low-noise, 4-channel simultaneous-sampling successive-approximation-register (SAR) analog-to-digital converter with differential, wide common-mode-range inputs, delivered in a 32-pin QFN (5x5 mm) package. Each of the four channels samples at up to 400 ksps, and the part operates from a single 5 V analog supply with an internal reference and internal reference buffer, eliminating the need for external precision reference components. A SAR ADC (Successive Approximation Register analog-to-digital converter) is a type of precision data converter that performs one binary bit decision per clock cycle using an internal capacitive DAC, a comparator, and a successive-approximation register. Within the broader signal-chain hierarchy, the LTC2344-16 belongs to the precision SAR ADC family, which sits between high-speed pipeline ADCs and lower-power delta-sigma ADCs, offering a balance of latency, channel count, and DC accuracy. ADI's SoftSpan™ technology allows per-conversion, per-channel selection of the analog input range, optimizing dynamic range across all four channels. Key features of the LTC2344HUH-16 include pin-selectable SPI CMOS (1.8 V to 5 V) or LVDS serial interfaces, 1 to 4 lanes of CMOS data output, 102 dB CMRR, ±1.25 LSB INL, no missing codes at 16 bits, 93.4 dB SNR, and an operating temperature range of -40 °C to +125 °C. The wide common-mode input range and high CMRR allow the analog inputs to directly digitize a variety of signals - including those riding on top of large DC bias or AC common-mode voltages - simplifying the front-end signal chain by removing driver amplifiers and level-shifters in many applications. Architecturally, each channel uses a precision charge-redistribution capacitive DAC combined with an internal low-drift reference and a high-CMRR input front end, enabling simultaneous sampling of all four channels with matched aperture delay. Throughput and bus width are software-configurable: in CMOS mode the user may select 1, 2, or 4 LVDS lanes, while in LVDS mode the converter delivers full 400 ksps/channel throughput to modern FPGAs. The integrated reference buffer preserves low noise and high PSRR even when multiple channels are sampling simultaneously, making the LTC2344HUH-16 well suited for multi-axis data-acquisition systems. Typical applications include multi-axis motor and motion control, industrial process control, test and measurement instrumentation, seismic and energy-exploration data acquisition, and high-speed medical imaging front ends. The combination of true simultaneous sampling, wide common-mode range, and per-channel span switching makes it especially attractive for multi-phase power-conversion feedback, vibration analysis, and phased-array sensor systems. When designing with the LTC2344HUH-16, ensure that the analog inputs remain within the datasheet common-mode and differential range for the selected SoftSpan range, and follow ADI's recommended layout for the exposed pad (EP) to maintain thermal performance and low digital crosstalk. Decouple the 5 V AVDD and the digital DVDD rails with low-ESR ceramic capacitors placed as close to the IC as possible. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, with data verified as of 2026-10-13.
LTC2344HUH-18 - 18-Bit Quad SAR ADC, 400ksps/ch | Analog Devices
The Analog Devices LTC2344HUH-18 is a quad, 18-bit, 400 ksps per channel differential SoftSpan successive approximation register (SAR) analog-to-digital converter (ADC) housed in a 32-pin QFN (5x5 mm) exposed-pad package. Each of the four simultaneous-sampling channels integrates a precision SAR core, an internal 2.048V reference, and a wide common-mode input stage that accepts differential inputs spanning rail-to-rail (0V to VREF or 0V to 2*VREF), making the part suitable for high-density data acquisition boards where PCB real estate is at a premium. A SAR ADC is a successive-approximation analog-to-digital converter: it performs one bit-trial per clock cycle against an internal capacitive DAC, converting analog input to digital code in N cycles for N bits of resolution. SAR ADCs combine low latency, deterministic behavior, and excellent DC accuracy, which is why they dominate multi-channel precision instrumentation, oscilloscope digitizers, and industrial process-control front ends. The LTC2344-18 sits in the hierarchy: SAR ADC -> ADC -> data converter -> signal chain IC -> semiconductor. Key features include 4 differential simultaneous-sampling inputs, software-configurable per-channel input range (SoftSpan from ±10.24V to 0V–5V using internal reference scaling), pin-selectable SPI CMOS (1.8V to 5V) or LVDS serial interfaces, and 1 to 4 CMOS output lanes for bus-width optimization. Typical SNR of 95 dBFS and INL of ±2.5 LSB (max) support demanding measurement-grade applications. The architecture pairs an analog 5V supply (AVDD) with a separate digital 1.8V to 5V supply (OVDD), allowing the ADC to digitize ±10V signals while directly interfacing to low-voltage FPGAs or microcontrollers. The internal reference and reference buffer reduce BOM count by eliminating external REF02-class components. Typical applications include multi-axis motor control feedback, programmable logic controller (PLC) analog input modules, data acquisition systems (DAQ), instrumentation and test equipment, and high-precision multi-channel sensor signal conditioning. The wide common-mode range simplifies level shifting when digitizing bridge sensors, thermocouples, or current-sense amplifiers referenced to a mid-supply. When designing with this part, place the analog and digital decoupling capacitors as close as possible to AVDD and OVDD pins, and provide a solid ground plane beneath the exposed pad to keep the thermal resistance (around 40 C/W) within bounds. The SoftSpan input range should be configured per channel after the conversion starts; the LVDS interface option requires a 100 ohm termination at the receiver. This page synthesizes distributor pricing, drop-in same-package alternatives drawn from the Analog Devices LTC23xx family, and practical design notes that complement the manufacturer's datasheet.
LTC2345CUK-18 - Octal 18-bit 200kSps Diff SoftSpan ADC | ADI
The Analog Devices LTC2345CUK-18 is an octal, 18-bit, 200 kSps differential SoftSpan successive approximation register (SAR) analog-to-digital converter housed in a 48-lead QFN (7x7) package. It delivers ±5 LSB INL, no missing codes at 18-bit resolution, and 91.8 dB SNR across eight differential input channels with wide input common-mode range. The device supports pin-selectable SPI CMOS (1.8 V to 5 V) and LVDS serial interfaces for flexible digital connectivity. Operating from a single 5 V low-voltage supply with integrated reference and buffer, the part is tailored to wide-input-range multi-channel data acquisition. A SoftSpan ADC is a successive approximation converter whose input voltage range can be reconfigured on a per-conversion, per-channel basis via internal programmable gain stages. Within the data-converter hierarchy, SAR ADCs sit between flash converters (fastest, lowest resolution) and sigma-delta ADCs (highest resolution, lower bandwidth). The LTC2345CUK-18 occupies the multi-channel, medium-resolution, low-latency niche where simultaneous acquisition of several signals is required without the latency penalty of sigma-delta. Key differentiating features include eight truly differential input channels sampled through an 8-channel simultaneous-sampling front end, per-conversion SoftSpan range selection across multiple bipolar and unipolar spans, and an integrated 2.048 V reference with buffer that eliminates external reference components. The QFN-48 (UK suffix) 7x7 mm package with exposed pad provides a low thermal resistance path and compact PCB footprint. Typical applications include multi-axis industrial process control, multi-channel instrumentation, optical networking power monitoring, and programmable logic controller (PLC) analog front ends. The simultaneous-sampling capability is decisive in phased-array and vibration analysis where channel-to-channel skew would corrupt the measurement. As of 2026-10-13 pricing is held in distributor stock at DigiKey, Mouser, and authorized partners. When designing with the LTC2345CUK-18, ensure the exposed pad is soldered to a continuous ground plane for thermal dissipation and reference decoupling. Reject NMC pins by tying them to known logic levels per the datasheet, and route the LVDS or SPI traces as 50 ohm controlled-impedance differential lines if LVDS mode is selected. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the standalone manufacturer datasheet.
LTC2348CLX-16 - Octal 16-Bit 200ksps SAR ADC | Analog Devices
The Analog Devices LTC2348CLX-16 is an octal, 16-bit, 200ksps per-channel simultaneous-sampling successive approximation register (SAR) ADC with differential inputs and a wide input common-mode range, packaged in a 48-pin LQFP (7x7). It features eight independent SoftSpan inputs that can each be reconfigured on a per-conversion basis, integrated precision buffers, an internal reference, and a 5V low-voltage analog supply with flexible high-voltage supplies for the input front-end. The wide common-mode range and 118dB CMRR allow the analog inputs to directly digitize a variety of industrial signal levels without external level translation. A successive approximation register ADC is a precision data converter architecture that performs a binary search on the input voltage using a high-precision DAC and comparator to produce a digital code in N conversion cycles for N bits of resolution. SAR ADCs are valued for low latency, no pipeline delay, excellent DC accuracy, and inherent per-sample determinism, which makes the LTC2348 family particularly well suited to multi-channel data-acquisition systems where eight channels must be sampled synchronously to preserve phase and amplitude relationships. SoftSpan further extends the architecture by allowing each channel's input range to be reconfigured cycle-by-cycle to one of several software-selectable spans. Key specifications include 16-bit resolution with no missing codes, +/-1LSB INL (max), 94.4dB SNR, and 200ksps throughput per channel on all eight channels simultaneously. The differential wide-common-mode input structure supports +/-10.24V true bipolar signals when paired with the appropriate high-voltage supply, and the device provides per-channel input span reconfiguration for mixed-range acquisition. Integrated reference and buffer simplify the analog supply tree and reduce external BOM. In multi-channel industrial applications, the simultaneous-sampling SAR topology captures all eight channels in lock-step with sub-microsecond aperture timing, eliminating inter-channel skew that would otherwise corrupt phase-sensitive measurements. Designers can pair the converter with an FPGA or DSP for digital signal processing, and leverage the SoftSpan range reconfiguration to mix high-level and low-level sensors on a single ADC chip. When laying out the PCB, keep analog input traces short and symmetric, place the internal reference decoupling capacitor close to the REF pin, and provide a solid ground plane under the LQFP body. Use a dedicated low-noise LDO for the 5V analog rail and isolate it from digital switching supplies to preserve the 94.4dB SNR. This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design notes not found in the manufacturer datasheet, giving engineers a single source for both selection and design-in guidance.
LTC2348HLX-16 - Octal 16-Bit 200ksps SAR ADC | Analog Devices
The Analog Devices LTC2348HLX-16 is a 16-bit, low-noise, 8-channel simultaneous sampling successive approximation register (SAR) analog-to-digital converter (ADC) with differential, wide common-mode range inputs, housed in a 48-pin LQFP (7x7) package. It supports ±10.24 V true bipolar SoftSpan inputs, 200 ksps per channel throughput, and 94.4 dB SNR with 118 dB CMRR per the manufacturer datasheet. A successive approximation register (SAR) ADC is a type of data converter that performs a binary search to digitize an analog input one bit at a time using an internal capacitive DAC and a comparator. SAR ADCs are prized for low latency, deterministic latency, and excellent DC accuracy, occupying a middle position in the converter hierarchy: SAR ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor. The LTC2348 family is positioned for high-precision multi-channel applications where simultaneous sampling across channels is required, such as in polyphase power metering and multi-axis industrial control. Key features include independent per-channel SoftSpan input ranges (±10.24 V, 0 V to 10.24 V, ±5.12 V, 0 V to 5.12 V, and additional ranges), a wide input common-mode range that allows direct digitization of many signals without front-end signal conditioning, ±1 LSB INL with no missing codes at 16 bits, and an internal 2.048 V reference with buffer. The 48-pin LQFP-48 (7x7) package exposes separate analog and digital supply pins (4.75 V to 5.25 V), an SPI-compatible serial interface, and an extended automotive temperature grade of -40 °C to +125 °C per the H-grade designation. The architecture uses eight simultaneous-sample-and-hold front ends that capture all channels on the same CONVST rising edge, eliminating inter-channel skew. A flexible external or internal reference and a per-channel sequencer allow each of the eight conversions to be configured independently, simplifying systems where channel ranges differ across a single scan. Typical applications include polyphase energy and power metering, multi-axis motor control and industrial PLC analog front ends, data acquisition systems with high common-mode voltages, and medical instrumentation requiring simultaneous sampling. Because each channel can be independently ranged, a single LTC2348-16 can replace multiple ADCs in mixed-voltage systems. When designing with this part, place the analog and digital decoupling capacitors as close as possible to their respective supply pins and route the analog and digital grounds back to a single point to preserve the 94.4 dB SNR. The internal reference and buffer simplify BOM cost, but designers who need lower drift across temperature can disable the buffer and drive REFIN with an external low-noise reference. This page synthesizes verified distributor pricing, drop-in pin-compatible alternatives drawn from the same LQFP-48 family, and practical PCB/grounding design notes that go beyond the manufacturer datasheet block diagram.
LTC2348HLX-18 - 18-Bit Octal SAR ADC, 200ksps, 48-LQFP | ADI
The Analog Devices LTC2348HLX-18 is an 18-bit, low-noise, 8-channel simultaneous-sampling successive approximation register (SAR) ADC with differential, wide common-mode-range inputs, offered in a 48-lead LQFP (7x7 mm) package. Each of the eight channels samples at up to 200 ksps and delivers 96.7 dB SNR with ±3 LSB INL and no missing codes at 18 bits. What is a SAR ADC? A successive-approximation-register analog-to-digital converter is a precision data-conversion architecture that uses a binary-search algorithm against an internal DAC to resolve an analog input one bit at a time. SAR ADCs sit in the signal-chain hierarchy between flash converters (fastest, lowest resolution) and sigma-delta converters (highest resolution, lower speed), and are prized for their deterministic latency, excellent DC accuracy, and low power per conversion. The octal simultaneous-sampling topology extends this precision to multi-axis or multi-phase systems by guaranteeing that all eight channels capture the same instant in time. Key features include pin-selectable SoftSpan input ranges on a per-channel, per-conversion basis, ±10.24 V true-bipolar differential inputs with 118 dB CMRR, an internal 2.048 V reference with 2X buffer (external reference supported), and a serial interface selectable between 1.8 V to 5 V CMOS SPI and LVDS with one to eight output lanes. The wide common-mode input range allows the ADC to directly digitize signals riding on high voltages, eliminating external level-shift circuitry in many applications. The architecture combines eight simultaneously-sampling track-and-hold front-ends with a shared SAR core, internal reference/buffer, and configurable logic. SoftSpan allows the user to switch input ranges per conversion, optimizing dynamic range channel-by-channel, while the wide common-mode range and 118 dB CMRR simplify the analog front-end for industrial signal chains. Typical applications include multi-axis motor control and servo drives, three-phase power-quality monitoring, simultaneous-sampled data acquisition (DAQ) modules, medical multi-channel instrumentation, and ATE pin electronics. The wide input common mode and bipolar ranges make it well-suited to industrial 24 V / ±15 V signal environments. A primary design consideration is power-supply sequencing: the LTC2348HLX-18 requires a 5 V low-voltage supply and flexible high-voltage supplies. Decoupling must be placed close to each supply pin, and reference bypass capacitors must follow the datasheet's recommended network to achieve the rated 96.7 dB SNR. This page synthesizes distributor pricing, drop-in same-package alternatives from the LTC2348 family, and practical design notes not aggregated in a single location on the manufacturer's datasheet.
LTC2351CUH-14 - 14-Bit 1.5Msps 6-Ch Simultaneous-Sampling ADC | ADI
The Analog Devices LTC2351CUH-14 is a 14-bit, 1.5Msps analog-to-digital converter (ADC) with six simultaneously sampled differential inputs, housed in a 32-pin QFN (5mm x 5mm) package. It draws only 5.5mA from a single 3V supply, and a sleep shutdown mode further reduces power consumption to 12uW, making it ideal for portable and multi-channel data-acquisition systems. An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes for processing by microcontrollers, DSPs, or FPGAs. Multi-channel simultaneous-sampling ADCs such as the LTC2351CUH-14 are a specialized subclass of successive-approximation-register (SAR) ADCs designed for applications where the relative phase between channels must be preserved — for example, three-phase power monitoring, multi-axis vibration analysis, and phased-array beamforming. The LTC2351CUH-14 belongs to the power management and signal-chain IC hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Key features of the LTC2351CUH-14 include six differential input channels sampled simultaneously at up to 1.5Msps per channel, a single 3V analog supply operation, 12uW sleep-mode power, and an integrated track-and-hold per channel. The device accepts differential inputs well suited to bridge sensors, current shunts, and direct connection to operational amplifiers. Its 32-lead 5x5mm QFN package provides a compact footprint suitable for portable instrumentation and high-density PCB layouts. The LTC2351CUH-14 is built on a low-power CMOS SAR architecture with internal reference and six dedicated sample-and-hold amplifiers that capture all channel voltages on the same clock edge, eliminating inter-channel skew. A standard SPI/serial interface streams conversion results to the host controller, and a dedicated CONVST pin initiates conversion across all six channels synchronously. Typical applications include three-phase power-quality monitoring, multi-axis industrial vibration analysis, portable medical instrumentation, simultaneous multi-sensor data acquisition, phased-array ultrasound receivers, and multi-channel sonar / radar front-ends. The wide dynamic range and low power make the part suitable for both battery-powered and line-powered instruments. When designing with the LTC2351CUH-14, ensure the analog input common-mode voltage lies within the input range of the SAR core, and add anti-alias filtering on each differential pair. Decouple the 3V analog supply with a 10uF ceramic + 0.1uF X7R combination placed within 5mm of the supply pin to minimize ADC reference noise and improve spurious performance. This page synthesizes verified distributor pricing, drop-in alternative MPNs, and practical design notes drawn from the manufacturer datasheet and reference designs - content not consolidated on distributor product pages.
LTC2351CUH-14#PBF - 14-Bit 1.5Msps 6-Ch Simultaneous-Sampling ADC | ADI
The Analog Devices LTC2351CUH-14#PBF is a 14-bit, 1.5 Msps analog-to-digital converter with six simultaneously sampled differential inputs, housed in a 32-pin (5 mm x 5 mm) QFN package. It draws only 5.5 mA from a single 3 V supply and features a sleep shutdown mode that reduces power consumption to 12 uW, making it well suited for portable and multi-channel data-acquisition applications. Per the manufacturer datasheet, the device integrates six independent sample-and-hold amplifiers followed by a single shared 14-bit successive-approximation ADC core that sequentially converts each held channel at the full 1.5 Msps conversion rate. A SAR (Successive Approximation Register) ADC is a type of data converter that converts an analog input into a digital code by iteratively comparing the input against a precision DAC and a reference voltage. In system hierarchy, the LTC2351-14 belongs to: SAR ADC -> ADC -> data converter -> signal chain IC -> analog/mixed-signal semiconductor. SAR ADCs are valued for their deterministic latency, lack of pipeline delay, and excellent DC accuracy, which makes the simultaneous-sampling variant especially useful when the relative phase between channels must be preserved (such as in three-phase power metering or vibration analysis). Key features include six differential inputs sampled on the same clock edge (preserving inter-channel phase), a serial LVCMOS-compatible interface, an internal 2.5 V reference (with provision for an external reference), and an input common-mode range that accommodates both unipolar and bipolar signals when paired with appropriate driver circuits. The 32-lead QFN package provides a low thermal-resistance path and a compact 5 mm x 5 mm footprint suitable for space-constrained PCB designs. Typical applications include multiphase power monitoring, industrial process control and instrumentation, portable and handheld test gear, simultaneous data acquisition systems, vibration and modal analysis, and motor control feedback. The wide input common-mode range and differential architecture also simplify connection to bridge sensors and current-shunt monitors. A practical design tip is to place 0.1 uF ceramic bypass capacitors close to each supply pin and to keep the analog input traces short and symmetric, because aperture-time mismatch between channels at 1.5 Msps can otherwise manifest as inter-channel skew that degrades phase-sensitive measurements. This page synthesizes distributor pricing, drop-in alternatives, and design notes not found in the manufacturer datasheet, giving engineers a single source for evaluating, sourcing, and laying out the LTC2351CUH-14#PBF.
LTC2351CUH-14#TRPBF - 14-Bit 1.5Msps 6-Ch SAR ADC | Analog Devices
The Analog Devices LTC2351CUH-14#TRPBF is a 14-bit, 1.5 Msps successive-approximation analog-to-digital converter with six simultaneously-sampled differential input channels, housed in a 32-pin QFN (5 mm x 5 mm) package. The device operates from a single 3 V supply, drawing only 5.5 mA, and integrates a per-channel sample-and-hold amplifier so all six channels are sampled on a single CONV rising edge. A successive-approximation register (SAR) ADC is a precision data converter that performs a binary search against an internal DAC on each conversion cycle. Unlike pipeline or delta-sigma ADCs, SAR converters deliver a single-cycle latency with no digital filtering delay, making them well suited to multiplexed data acquisition, motor control loops, and multi-phase power monitoring where the relative timing between channels must be preserved. The LTC2351-14 family is positioned within Analog Devices' precision SAR product line for low-power, multi-channel, simultaneous-sampling applications. Key specifications include 14-bit resolution, 1.5 Msps per-channel throughput, six differential inputs sampled simultaneously, 5.5 mA typical supply current at 3 V, and an integrated shutdown mode that drops quiescent power to 12 uW. The 32-pin QFN (5x5) package provides a compact footprint and low thermal resistance for portable and densely-populated PCBs. Each channel features its own dedicated S/H amplifier, eliminating the skew between channels that would otherwise occur with a multiplexer-front-end architecture. Architecturally, the LTC2351-14 uses a capacitive charge-redistribution DAC core with an inherent sample-and-hold on every channel. The device accepts bipolar differential inputs of up to +/-2.048 V when using the on-chip reference and 3 V supply, or larger true bipolar ranges with an external reference. The serial LVTTL interface outputs the conversion result and per-channel data framing, simplifying connections to FPGAs, DSPs, and microcontrollers. Typical applications include industrial multi-phase power metering, three-phase motor control, simultaneous vibration and acoustic monitoring, multi-axis instrumentation, portable medical data acquisition, and any system that requires synchronized sampling across multiple analog inputs. The low 5.5 mA supply current also enables battery-powered multi-channel data loggers. When designing with this part, bypass the VDD pins with 10 uF and 0.1 uF ceramic capacitors placed as close to the package as possible, keep analog and digital grounds separated back at a single star point under the exposed pad, and tie the exposed paddle to analog ground for lowest noise. Driving the CONV input with a clean, low-jitter edge is essential to preserving simultaneous-sampling accuracy across channels. This page consolidates distributor stock and price data, drop-in same-package alternatives, and practical design notes drawn from the manufacturer datasheet and reference designs - information gain not bundled on the OEM datasheet alone.
LTC2351HUH-14#TRPBF - 14-Bit, 1.5Msps, 6-Ch Simultaneous-Sampling ADC | Analog Devices
The Analog Devices (formerly Linear Technology) LTC2351HUH-14#TRPBF is a 14-bit, 1.5 Msps analog-to-digital converter (ADC) with six simultaneously sampled differential inputs, housed in a 32-pin QFN (5 mm x 5 mm) package. Operating from a single 3 V supply, the device draws only 5.5 mA and integrates six track-and-hold amplifiers plus a 14-bit successive-approximation register (SAR) ADC core to preserve phase information across all six channels. A simultaneous-sampling SAR ADC is a converter that captures multiple analog channels on a common sampling edge, eliminating the inter-channel time skew inherent to multiplexed ADCs. Within the power-management IC family, the LTC2351 belongs to the data-converter hierarchy: ADC -> successive-approximation ADC -> simultaneous-sampling SAR ADC -> integrated multi-channel data acquisition IC. This category is foundational for any application that requires precise temporal correlation between multiple analog signals. Key specifications include a 1.5 Msps aggregate throughput, 5.5 mA typical supply current, 12 uW sleep-mode shutdown current, and six true-differential input channels. The device supports a single 3 V analog supply and includes an internal 2.5 V reference (with optional external reference drive), along with a serial LVCMOS-compatible interface that simplifies the digital connection to FPGAs, DSPs, or microcontrollers. Architecturally, each of the six input channels has its own dedicated track-and-hold amplifier that samples on the same CONVST edge, then sequentially converts through the shared 14-bit SAR core. This topology preserves full-scale input range while keeping the die small and power consumption low compared with six discrete ADCs. The integrated 2.5 V reference can be overdriven with an external reference for applications requiring tighter absolute accuracy or higher stability. Typical applications include three-phase power metering and motor-control feedback, multi-axis industrial motion control, portable and battery-powered instrumentation, and simultaneous multi-channel data acquisition boards. The combination of low 5.5 mA supply current and 12 uW sleep mode makes the LTC2351 especially attractive for handheld, energy-conscious designs. When designing with this ADC, place the AVCC decoupling capacitors within a few millimeters of the supply pins and keep the analog input traces short and symmetric to preserve common-mode rejection. Use the sleep (SHDN) pin aggressively between conversion bursts in low-duty-cycle applications to drop system consumption to the 12 uW range, which is roughly 460x lower than the active 5.5 mA. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical PCB-layout design notes not collected in the manufacturer datasheet, giving engineers a single reference for evaluation and sourcing.