FPGA & CPLD
Produtos (6666)
EPM9560RC304C-3 - MAX 9000 CPLD, 560 Macrocells, 304-Pin RBGGA | Altera
The Altera (Intel) EPM9560RC304C-3 is a high-density MAX 9000 family Complex Programmable Logic Device (CPLD) housed in a 304-pin RBGGA (Rugged Ball Grid Array) package with 560 logic elements (macrocells), 12,000 usable gates, and an in-system programmable, non-volatile EEPROM-based architecture. The device supports a pin-to-pin propagation delay of 3 ns (commercial speed grade) and operates from a single 5 V supply, with I/O standards including TTL and CMOS-compatible interfaces across 212 user I/O pins. Key features of the MAX 9000 family include the classic MAX (Multiple Array Matrix) interconnect structure with Logic Array Blocks (LABs) and a global Programmable Interconnect Array (PIA), in-system programmability via IEEE 1149.1 JTAG, and a built-in boundary-scan test capability that simplifies board-level test. The "C" suffix indicates commercial temperature grade (0 C to +70 C), the "RC" indicates a ceramic BGA package, and "-3" indicates the speed grade. The EPM9560 is the highest-density member of the MAX 9000 family and is widely deployed in legacy telecom, industrial control, and glue-logic applications where a non-volatile, deterministic CPLD is required. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with much higher gate density, providing deterministic timing and instant-on behavior from a single flash/EEPROM configuration cell. CPLDs sit alongside FPGAs in the programmable logic hierarchy, but are distinguished by their non-volatility, faster pin-to-pin deterministic timing, and lower power consumption at small logic capacities - making them ideal for control-plane logic, bus interfacing, address decoding, and state-machine replacement rather than high-density parallel DSP. Typical applications for the EPM9560RC304C-3 include legacy telecom backplane glue logic, industrial control and factory automation, address decoding for microprocessor and DSP systems, bus-interface bridging (e.g., PCI to local bus), and replacement of multiple discrete TTL/CMOS glue-logic ICs. The MAX 9000 family was one of the most widely deployed CPLD families of the late 1990s and early 2000s and is still in use today in long-lifecycle industrial and military systems. When designing with the EPM9560RC304C-3, designers should note that the device is part of an older MAX 9000 generation - Altera/Intel MAX II, MAX V, and MAX 10 families offer newer non-volatile CPLD alternatives with lower power and lower cost. However, for true pin-compatible drop-in replacements on existing 304-pin BGA layouts, the EPM9560RC304-15, EPM9560RC304-10, and EPM9560RC304-20 speed-grade variants are functionally identical. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on a single manufacturer page.
EPM9560RC340-15 - MAX 9000 CPLD, 560 Macrocells, 15ns | Altera
The Altera EPM9560RC340-15 is a high-density, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 560 macrocells and approximately 12,000 usable gates with a 15 ns pin-to-pin delay in a 340-pin RQFP package. It is built on a third-generation Multiple Array MatriX (MAX) architecture and supports 5.0V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. A Complex Programmable Logic Device (CPLD) is a non-volatile, EEPROM- or flash-based integrated circuit that combines multiple PAL/GAL-style logic blocks with a programmable interconnect matrix, providing deterministic timing, instant-on operation, and high fan-in per output. CPLDs sit below FPGAs in the programmable logic hierarchy: FPGAs offer higher logic density and SRAM-based reconfigurability, whereas CPLDs excel at glue logic, bus decoding, state machines, and power-sequencing applications where fast, predictable propagation delay and zero-configuration boot time matter more than raw gate count. Key features of the EPM9560RC340-15 include a 15 ns maximum pin-to-pin propagation delay (tPD), 5.0V VCC operation (4.75V to 5.25V tolerance), up to 212 user I/O pins, JTAG-based boundary-scan test per IEEE 1149.1, and 12,000 gates of MAX architecture logic. The 340-pin RQFP (Reduced Quad Flat Pack) package provides surface-mount integration with thermal performance suitable for industrial operating conditions (0C to +70C commercial range). Internally, the device is organized as multiple Logic Array Blocks (LABs) interconnected by a programmable switch matrix, with each macrocell containing programmable AND/OR arrays plus a configurable flip-flop. The EEPROM process technology ensures reprogrammability without external memory, while the JTAG port enables in-system reconfiguration, production-line programming, and board-level boundary-scan testing per IEEE 1149.1. Typical applications include high-density glue logic for microprocessor/microcontroller systems, bus-interface bridging (e.g., 8-bit to 16-bit or 16-bit to 32-bit translation), state-machine controllers, and replacement of multiple discrete PAL/GAL devices in industrial control and telecommunications equipment. With 212 user I/Os and 560 macrocells, the EPM9560 is well suited to consolidating dozens of small logic functions onto a single programmable device, simplifying PCB layout and reducing BOM count. When designing with this device, allocate sufficient I/O headroom and verify JTAG chain topology against the IEEE 1149.1 specification before layout finalization. The MAX 9000 family uses Altera legacy MAX+PLUS II development tooling, which is now distributed by Intel FPGA; designers should confirm tool availability for new projects. This page synthesizes distributor availability, same-package drop-in alternatives from the Site MPN list, and practical design notes for the MAX 9000 architecture not found in the standalone datasheet.
EPM9560RCRC304-15 - MAX 9000 CPLD 560 Macro Cells | Altera
The Altera EPM9560RCRC304-15 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates and 560 macro cells with a 15 ns pin-to-pin propagation delay, housed in a 304-pin RQFP (PowerQuad) package. It is a 5.0 V EEPROM-based programmable logic device built on Altera's third-generation Multiple Array MatriX (MAX) architecture. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of a field-programmable gate array with the non-volatile, instant-on behavior of a PAL. In the product hierarchy, a CPLD sits between simple PLDs and FPGAs: CPLD -> programmable logic device -> digital logic IC -> semiconductor. MAX 9000 devices use EEPROM configuration cells, so they retain their design without an external configuration memory and are live at power-up, unlike SRAM-based FPGAs. Key features of the EPM9560RCRC304-15 include 560 macro cells, 12,000 usable gates, a 15 ns pin-to-pin logic delay, and 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. The device supports up to 216 user I/O pins and operates from a single 5 V supply, making it directly compatible with legacy 5 V TTL and CMOS logic levels. The MAX 9000 architecture uses a hierarchical Multiple Array MatriX of logic array blocks (LABs) interconnected by a fast, predictable routing structure. This deterministic interconnect gives fixed, data-sheet-guaranteed timing independent of placement and routing, which is a major advantage over SRAM FPGAs for glue-logic, state-machine, and bus-interface designs where timing closure must be repeatable. Typical applications include legacy industrial control backplanes, 5 V bus bridging and address decoding, telecommunications line-card glue logic, test and measurement instrumentation, and replacement of discrete 74-series logic in existing designs. The 304-pin RQFP package provides high I/O density for wide bus interfaces. When designing with this device, note that it is a mature, non-volatile 5 V part: verify availability of the MAX+PLUS II development toolchain and confirm the JTAG ISP chain before committing a new design. Because the part is EOL/obsolete at the manufacturer, second-source or drop-in alternatives should be qualified early. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and migrating the EPM9560RCRC304-15.
EPM9560RI205-15 - MAX 9000 CPLD, 6K Gates, 15ns | Altera
The Altera EPM9560RI205-15 is a member of the MAX 9000 family of high-performance CMOS EEPROM-based Complex Programmable Logic Devices (CPLDs) implementing up to 6,000 usable gates, housed in a 205-pin RQFP package with a 15 ns pin-to-pin propagation delay. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, the device integrates multiple Logic Array Blocks (LABs) and a programmable interconnect network to deliver deterministic, high-speed combinational and registered logic for glue-logic and bus-interface applications. A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on semiconductor that combines the integration density of an FPGA with the deterministic timing and low power of a traditional SPLD. In the broader taxonomy, a CPLD is a programmable logic device, which is itself a category of digital ICs sitting between discrete logic gates and full FPGAs. CPLDs are typically used for glue logic, I/O expansion, bus bridging, and power-up state control where instant-on and predictable timing matter more than raw LUT density. Key features of the EPM9560RI205-15 include 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, 212 macrocells distributed across LABs, and dedicated I/O pins with programmable drive strength and slew-rate control. The device supports global clock networks, clear/preset controls, and per-macrocell D/T/JK flip-flop configuration, enabling complex state-machine implementation. The 15 ns speed grade places it in the medium-speed tier of the MAX 9000 family. Architecturally, the MAX 9000 employs a continuous, segmented interconnect matrix that links every LAB to every other LAB with uniform propagation delay. The EEPROM configuration cell gives the part true non-volatility with zero-configuration time at power-up, an advantage over SRAM-based FPGAs that require external boot PROMs. Per-pin JTAG boundary-scan and a built-in IEEE 1149.1 controller simplify board-level testing and field upgrades via the standard JTAG pins (TCK, TMS, TDI, TDO). Typical applications include bus interface bridges (e.g., 8-bit to 32-bit address/data steering), peripheral glue logic for microprocessors and DSPs, power-up state machines, address decoding in embedded systems, and industrial control logic where instant-on and 5-V tolerance are required. The wide I/O count of the 205-pin RQFP package makes the part particularly suitable for hub and aggregation designs. When designing with the EPM9560RI205-15, observe the 5.0-V VCCIO tolerance and provide adequate decoupling - at least 0.1 uF ceramic on every VCC/ground pair within 100 mils of the package pin. Use the JTAG chain to retain ISP capability even after PCB assembly. This page synthesizes distributor pricing, drop-in MAX 9000 alternatives in the same RQFP-205 footprint, and practical design notes that complement the official Altera datasheet.
EPM9560RI208-10 - 12K-Gate MAX 9000 CPLD, 10ns, 208-Pin RQFP
The Intel (formerly Altera) EPM9560RI208-10 is a high-density, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, fabricated on an advanced 0.5 µm CMOS technology. It provides approximately 12,000 usable gates, 560 macrocells, and pin-to-pin delays as fast as 10 ns with counter frequencies up to 144 MHz, all housed in a 208-pin Power Quad Flat Pack (RQFP) surface-mount package rated for the industrial temperature range (-40 °C to +85 °C). A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic device that combines multiple PAL-like macrocell blocks connected through a central programmable interconnect array (PIA). CPLDs sit between small SPLDs/GALs and large SRAM-based FPGAs in the programmable logic hierarchy: they offer deterministic 10 ns-class pin-to-pin timing, ISP via JTAG, and zero-configuration boot time, making them ideal for glue logic, bus decoding, and control-plane state machines. The MAX 9000 family extends the MAX 7000 architecture to higher densities by tiling more Logic Array Blocks (LABs) onto a unified PIA fabric. Key features of the EPM9560RI208-10 include the 10 ns tPD speed grade, 560 macrocells distributed across LABs, 212 user I/O pins (typical for the 208-RQFP package), in-system programmability via the IEEE 1149.1 (JTAG) interface, 5.0 V VCCINT operation, and a programmable power-saving mode that reduces Icc by up to 50 % on unused macrocells. The 208-pin RQFP package provides generous board-routing room for legacy 5 V designs that have long since moved off SOIC/QFN footprints. Architecturally, the device integrates a global PIA, multiple LABs each containing 16 macrocells, I/O control blocks, and four dedicated input pins that feed the global clock/clear network. The EEPROM configuration cell supports 100 erase/program cycles and is retained for at least 10 years per the legacy MAX 9000 datasheet. Boundary-scan JTAG, an open-drain ISP interface, and PCI-compliant I/O make the part a common choice for 5 V bus-interface bridges. Typical applications include 5 V PCI bus interface glue logic, address decoding and wait-state generation in 68k/8051/x86 embedded systems, industrial motor-control state machines, and legacy telecommunications backplane controllers. Engineers often place the EPM9560RI208-10 between an asynchronous SRAM bank and a microcontroller to implement programmable timing, glue logic, or bus-width adapters. When designing with this device, observe the legacy 5 V I/O tolerance: it cannot be directly interfaced to 3.3 V logic without external level shifters or bus switches, and the 208-pin RQFP requires a generous PCB land pattern. Verify timing with the Quartus II legacy support package, since newer Quartus releases target modern Cyclone/MAX V families. This page consolidates distributor pricing and parametric data not always presented on a single manufacturer page.
EPM9560RI208-10N - MAX 9000 CPLD, 12K Gates, 208-Pin RQFP
The Altera (now Intel) EPM9560RI208-10N is a member of the MAX 9000 family of high-performance, in-system programmable CMOS EPLDs based on the third-generation Multiple Array MatriX (MAX) architecture. It integrates 12,000 usable gates, 560 macro cells, and a 16-macro-cell Logic Array Block (LAB) structure with 12,160 register bits, and it operates at a pin-to-pin propagation delay of approximately 10 ns. The device is housed in a 208-pin RQFP (Plastic Quad Flat Pack) package with 212 user I/Os and operates from a single 5V supply with in-system programmability via IEEE 1149.1 (JTAG) boundary scan. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the low cost and ease of use of PAL/GAL structures with the high integration and routing flexibility of FPGA-like fabric. Within the broader programmable logic taxonomy, the CPLD sits between simple PLDs (PAL, GAL) and high-density FPGAs, providing fast, deterministic pin-to-pin timing (predictable interconnect delays) with non-volatile EEPROM configuration memory. The MAX 9000 family, in particular, introduced the LAB-based interconnect scheme that became Altera's architectural hallmark for high-pin-count glue-logic designs. The key features that distinguish EPM9560RI208-10N include 560 macro cells, a maximum operating frequency of approximately 100-125 MHz (per the MAX 9000 family rating), 212 user I/Os, and a 5V core supply. The "RI" package suffix denotes the Industrial operating-temperature grade (-40C to +85C), and the "-10" speed grade specifies the 10 ns pin-to-pin delay. The "N" suffix indicates a lead-free, RoHS-compliant assembly. JTAG-based in-system programming enables field upgrades without removing the device from the board, and the on-chip EEPROM cells retain the configuration indefinitely without a separate boot PROM. Typical applications for the EPM9560RI208-10N include 32-bit PCI bus interface glue logic, high-speed address decoding in embedded processor systems, bus isolation and multiplexing (e.g., between a DSP and a memory bus), state-machine controllers for industrial automation, and glue logic between disparate logic families in mixed-voltage designs. Designers choose the MAX 9000 family specifically when deterministic timing, non-volatility, and high pin count are required without the complexity of an FPGA. With 12K gates and 212 I/Os, the EPM9560 handles wide bus interfaces and parallel control tasks more elegantly than multiple discrete PLDs. When designing with this device, allow adequate ground and VCC pins on both sides of the package to ensure low-impedance power delivery for the simultaneous-switching output currents typical of 208-pin bus glue designs. Use the JTAG chain to program the device in-system, but observe the manufacturer's recommended 5V supply ramp and decoupling network (typically 0.1 uF ceramic plus 10 uF bulk per VCC pin group) to keep the EEPROM programming voltage well-regulated. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
EPM9560RI208-15 - 560-Macrocell MAX 9000 CPLD, 208-Pin RQFP | Intel
The Intel (formerly Altera) EPM9560RI208-15 is a high-performance, 560-macrocell CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, packaged in a 208-pin Power Quad Flat Pack (RQFP) with industrial temperature grading. It is built on the third-generation Multiple Array MatriX (MAX) architecture, supports 153 user I/O lines, and operates at a typical internal frequency of 145 MHz with a pin-to-pin propagation delay of 11.4 ns (commercial) to 15 ns (industrial -15 speed grade). A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like logic blocks on a single die with a global interconnect matrix. In the system hierarchy, CPLDs sit between simple SPLDs (PAL/GAL) and FPGAs: they offer deterministic, tCO-class timing, instant-on configuration from on-chip EEPROM, and high-drive I/O suited to bus-interface and glue-logic roles. The MAX 9000 family extends the classic MAX architecture to densities between 5,000 and 12,000 usable gates, positioning the EPM9560 as the mid-to-high density member with 12,000 typical gates. Key features of the EPM9560RI208-15 include in-system programmability (ISP) via JTAG (IEEE 1149.1), 5.0 V VCCIO-tolerant multi-volt I/O (3.3 V or 5 V mixed-mode), 16 macrocell LABs of 16 macrocells each, four global clock pins, programmable power-saving per macrocell, and JTAG boundary-scan testability. The 208-pin RQFP gull-wing package gives a thermal resistance suitable for 0 to 70 °C commercial environments in the -15 speed grade. The architecture uses a high-performance CMOS EEPROM process, providing non-volatile configuration retention, fast in-system erase/program, and predictable combinational/sequential logic. The interconnect is a continuous, fast-path Programmable Interconnect Array (PIA) that routes any LAB output to any other LAB input without contention, simplifying timing closure for control and bus-interface designs. Typical applications include bus-interface glue logic (PCI bridges, address decoding), 5 V to 3.3 V level shifting, microcontroller peripheral expansion, state-machine controllers, JTAG-based boundary-scan boards, and industrial control glue where instant-on, non-volatile boot is required. With 153 user I/Os in a 208-pin footprint, the EPM9560 is well matched to wide-bus interface designs. When designing with this device, observe the 5 V nominal supply tolerance (typically 4.5 V to 5.5 V), provide adequate decoupling (0.1 µF per VCC pin plus bulk), and follow Altera MAX 9000 JTAG ISP guidelines for in-system programming. The MAX+PLUS II or Quartus II toolchain (legacy) is required for design entry, fitting, and verification. This page synthesizes distributor pricing, EPM9560 family cross-references, drop-in pin-compatible same-brand alternatives (EPM9560 family speed/package variants), and practical design notes not consolidated in any single manufacturer document.
EPM9560RI208-15N - MAX 9000 EPLD, 208-Pin RQFP, 15ns | Altera
The Altera EPM9560RI208-15N is a high-performance CMOS EEPROM-based programmable logic device from the MAX 9000 family, built on third-generation Multiple Array MatriX (MAX) architecture. Delivered in a 208-pin RQFP (Ruggedized Quad Flat Pack) package with 5.0-V in-system programmability, the device integrates 216 user I/Os, 356 pins, and a maximum internal frequency of 145 MHz with a propagation delay of 11.4 ns at the -15 speed grade. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural density of a PLD with on-chip EEPROM configuration memory. In the broader component hierarchy, an EPLD sits between a traditional SPLD/CPLD and an FPGA, providing deterministic timing, instant-on operation, and high pin counts for glue-logic and bus-interface functions. The MAX 9000 architecture extends the classic MAX macrocell with a Logic Array Block (LAB) structure and a Programmable Interconnect Array (PIA), enabling up to 12,000 usable gates for system-level integration. Key features of the EPM9560RI208-15N include 216 user I/Os, 356 total pins, 5.0-V in-system programmability via IEEE 1149.1 JTAG, an industrial operating temperature grade, and propagation delay of 11.4 ns (15 ns speed grade). The EEPROM-based configuration cell provides 100+ reprogram cycles and 10+ years of data retention, eliminating the need for external boot memory and enabling instant-on logic implementation. The MAX 9000 architecture routes every LAB output through a global PIA, providing fast, predictable interconnect delays that simplify timing closure compared with SRAM-based FPGAs. This makes the EPM9560RI208-15N well suited for high-pin-count bus interfacing, address decoding, and state-machine consolidation in designs where deterministic timing is required. Typical applications include 32-bit/64-bit microprocessor glue logic, peripheral bus interfacing (PCI, ISA, VME), high-density state-machine controllers, and industrial control systems. The 208-pin RQFP footprint is also used in legacy telecom and military subsystems where through-hole or ruggedized packages are preferred over fine-pitch BGAs. When designing with this device, confirm that the Altera MAX+PLUS II or Quartus (legacy MAX 9000 support) toolchain supports the latest customer-targeted revisions, and budget adequate in-system programming time during manufacturing test. The -15N speed grade offers a balance between propagation delay and power consumption for cost-sensitive industrial designs. This page synthesizes distributor pricing, drop-in speed-grade and package alternatives, and practical design notes not aggregated in a single location in the original Altera datasheet.
EPM9560RI208-20 - 560-Macrocell CPLD, 12K Gates, 20ns | Intel (Altera)
The Intel (formerly Altera) EPM9560RI208-20 is a high-density, high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 12,000 usable gates, 560 macrocells, and a pin-to-pin propagation delay of 20 ns in a 208-pin Power-Quad Flat Pack (RQFP) package. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, it integrates 16 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA) and supports 5.0-V in-system programmability (ISP) via a built-in IEEE Std. 1149.1 JTAG interface, eliminating the need for an external PROM. The device operates across the commercial and industrial temperature ranges with counter frequencies up to 100 MHz. A Complex Programmable Logic Device (CPLD) is a non-volatile, instantaneously-on programmable logic IC that combines multiple PAL/GAL-style macrocell blocks with a centralized interconnect fabric. CPLDs are used for glue logic, bus interfacing, state machines, address decoding, and power-up control logic where deterministic timing and zero-power standby are required. CPLDs sit in the programmable logic hierarchy alongside FPGAs, with CPLDs typically favored for low-to-moderate logic density, fast I/O response, and predictable timing closure. Key features include 560 macrocells across 16 LABs, 212 user I/O pins (208-pin RQFP package), 20 ns pin-to-pin combinatorial delay, 100 MHz internal counter frequency, and JTAG-based ISP. The EEPROM process technology delivers zero-power standby (no configuration memory refresh) and 100% AC/DC testing prior to shipment, supporting automotive, telecom, and industrial control designs. Architecturally, the MAX 9560 uses each LAB to host 16 macrocells with a shared expander product term pool, while the PIA routes signals between LABs and the I/O pins with predictable, fixed delays. This delivers faster timing closure than SRAM-based FPGAs because routing delays are bounded and uniform. Typical applications include industrial control and factory automation, telecommunications line cards and bus interfaces, automotive body electronics and ECU glue logic, networking routers and switches, military and aerospace control systems, and legacy PCI/ISA bus bridges. Designers continue to specify the EPM9560RI208-20 because the MAX 9000 family is mature, long-lived, and supported by Altera/Intel legacy design tools. When designing with this device, ensure the JTAG chain follows IEEE 1149.1 daisy-chain order (TDI -> EPM9560 -> TDO) and that 5.0-V tolerant I/O pins are not driven above VCCIO during programming. Decoupling: place 0.1 uF and 10 uF capacitors adjacent to each VCC pin, and follow MAX 9000 family recommended PCB layout guidelines for high-speed signal integrity. This page synthesizes distributor stock and pricing across 1 authorized distributor (Octopart), cross-references drop-in same-package alternatives within the MAX 9000 family, and provides design notes not duplicated in the manufacturer datasheet.
EPM9560RI208-20N - MAX 9000 CPLD 12K Gates 208-RQFP | Intel
The Intel (Altera) EPM9560RI208-20N is a MAX 9000 family EEPROM-based Complex Programmable Logic Device (CPLD) offering 12,000 usable gates, 560 macrocells, and a 20 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad/quad flat pack) package. It operates from a 5.0 V supply and supports in-system programmability (ISP) through the IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks and macrocells with a programmable interconnect matrix, allowing designers to implement custom digital logic without fabricating an ASIC. Within the semiconductor taxonomy, the MAX 9000 CPLD sits under programmable logic devices (PLDs), alongside FPGAs and simple PLDs (SPLDs), and is used for glue logic, bus interfacing, and state-machine control. The MAX 9000 architecture is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, fabricated on an advanced CMOS process with EEPROM configuration cells. This non-volatile EEPROM technology allows the device to retain its configuration without an external configuration memory, unlike SRAM-based FPGAs. The -20 speed grade provides a 20 ns pin-to-pin delay, while faster -15 and -10 grades reach 15 ns and 10 ns respectively, with counter speeds up to 144 MHz on the fastest grade. Key features include 5.0 V in-system programmability via the built-in JTAG interface, 560 macrocells, and support for the MAX+PLUS II development system, which offers schematic, VHDL, Verilog HDL, and AHDL design entry, compilation, logic synthesis, simulation, timing analysis, and device programming in a single integrated toolchain. Typical applications include industrial control glue logic, bus bridging and address decoding, telecommunications line-card control, test and measurement instrumentation, and legacy system maintenance where 5 V logic levels and non-volatile configuration are required. When designing with the EPM9560RI208-20N, note that the 5.0 V core and I/O supply requires careful power distribution and decoupling, and that the RQFP package demands adequate thermal relief and copper area for reliable solder joints. Because the device is EEPROM-based, it can be reprogrammed in-system, simplifying field upgrades. This page synthesizes distributor availability, drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for sourcing and designing with the EPM9560RI208-20N.
EPM9560RI208-20W - MAX 9000 CPLD, 12K Gates, 208-Pin | Intel
The Intel (formerly Altera) EPM9560RI208-20W is a high-density, high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 12,000 usable gates, 560 macrocells, and pin-to-pin delays as fast as 20 ns in a 208-pin RQFP (Power Quad Flat Pack) package. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, this device combines in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface with 5.0V core operation, making it suitable for legacy industrial, telecom, and embedded control designs. The -20 speed grade delivers counter frequencies up to approximately 100 MHz and tPD propagation delays of 20 ns. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between discrete glue logic and FPGAs in the design hierarchy. CPLDs use EEPROM or flash configuration memory, providing instant-on behavior at power-up without an external boot ROM. Within the broader programmable logic taxonomy, the EPM9560RI208-20W belongs to: CPLD -> programmable logic -> logic IC -> integrated circuit. The MAX 9000 family uses a hierarchical routing architecture with Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), which optimizes timing predictability for state machine and decoder applications. Key features include 560 macrocells arranged in 16 Logic Array Blocks (LABs) of 40 macrocells each, 212 user I/O pins, JTAG-based IEEE 1149.1 boundary-scan test support, and 5V in-system programmability. The device supports PCI-compatible I/O and offers multiple speed grades (-10, -12, -15, -20) for trade-off optimization. The 'W' suffix denotes industrial temperature range and specific package/qualification options per Altera ordering codes. From an architecture perspective, the MAX 9000 uses a coarse-grained macrocell structure where each macrocell contains a programmable AND/OR array with a configurable flip-flop. This differs from FPGA fine-grained look-up-table architectures and gives the MAX 9000 family superior performance for wide combinatorial and registered logic functions at the cost of lower logic density per silicon area. Typical applications include industrial control glue logic, telecom interface bridging, PCI bus interface controllers, address decoding and bus arbitration, motor control state machines, and legacy 5V system replacements. The wide 5V tolerance makes it compatible with older microprocessors and bus standards. When designing with this device, ensure your JTAG chain is properly terminated and consider using Altera's legacy MAX+PLUS II or Quartus II tools for synthesis and fitting. The 208-pin RQFP footprint requires substantial PCB area; verify your thermal design at high toggle rates. This page synthesizes distributor pricing, drop-in same-package alternatives from the MAX 9000 family, and practical design notes not collected in the manufacturer datasheet.
EPM9560RI210-15 - MAX 9000 CPLD 560 Macrocell | Altera
The Altera EPM9560RI210-15 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 560 macrocells, 12,000 usable gates, and a 15 ns pin-to-pin propagation delay, housed in a 210-pin RQFP (PowerQuad) package. It operates from a 5.0 V supply and provides 164 user I/O pins for high-density glue logic, bus bridging, and state-machine integration. A CPLD (Complex Programmable Logic Device) is a programmable logic IC built from an array of macrocells connected by a programmable interconnect matrix. Unlike an FPGA, a CPLD stores its configuration in non-volatile EEPROM/flash, is instantly active at power-up, and offers deterministic, fixed timing. In the logic hierarchy, a CPLD sits between simple PLDs (PAL/GAL) and FPGAs, and belongs to the broader programmable logic device (PLD) and semiconductor IC categories. The MAX 9000 family uses Altera's FastTrack Interconnect and MultiVolt I/O, allowing 5.0 V core operation with 3.3 V-compatible I/O. Key features of the EPM9560RI210-15 include 560 macrocells organized into 20 logic array blocks (LABs), 12,000 usable gates, 164 user I/O pins, and a 15 ns pin-to-pin delay (the -15 speed grade). The device supports in-system programmability (ISP) via the JTAG boundary-scan interface, enabling field upgrades without removing the part from the board. Its 210-pin RQFP package provides a high I/O-to-package ratio for dense backplane and bus-interface designs. The MAX 9000 architecture routes signals through a continuous FastTrack Interconnect, giving predictable, skew-controlled timing that simplifies static timing analysis. Each macrocell contains a programmable flip-flop with individual clock, clear, and preset control, supporting both registered and combinatorial logic. The EEPROM configuration retains its programmed state for over 20 years and is immune to single-event upsets, making the device suitable for industrial control and instrumentation. Typical applications include PCI and VME bus bridging, industrial automation controllers, telecommunications line-card glue logic, test-and-measurement instrumentation, and legacy system replacement where instant-on operation and deterministic timing are required. The 5.0 V core and MultiVolt I/O simplify interfacing to both 5 V and 3.3 V peripherals. When designing with the EPM9560RI210-15, note that the device is a mature, legacy MAX 9000 part; verify availability and consider pin-compatible MAX 9000 variants in the same 210-pin RQFP footprint for supply continuity. Provide adequate decoupling and follow Altera's recommended power-up sequencing for reliable ISP operation. This page synthesizes distributor availability, drop-in MAX 9000 alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for replacement and lifecycle decisions.
EPM9560RI240-10 - MAX 9000 CPLD, 560 Macrocells, 12K Gates | Altera
The Altera (Intel) EPM9560RI240-10 is a high-density, in-system programmable CMOS Complex Programmable Logic Device (CPLD) from the MAX 9000 family, offering 560 macrocells and 12,000 usable gates in a 240-pin RQFP (Power Quad Flat Pack) package. It is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, operates from a 5.0 V supply, and is specified for a 10 ns pin-to-pin propagation delay (-10 speed grade), making it suitable for high-performance glue-logic, bus interfacing, and state-machine replacement in legacy industrial and telecom designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL devices with the density of small FPGAs. The CPLD taxonomy places it under programmable logic devices -> logic ICs -> integrated circuits -> semiconductors. CPLDs typically feature deterministic timing, instant-on behavior from on-chip EEPROM, and high pin-to-pin drive strength - characteristics that make them ideal for decoder, encoder, and interface-bridging functions. Within the Altera MAX family hierarchy, the MAX 9000 sits above the legacy MAX 5000/7000 series and below the MAX II/MAX V modern families. Key features include 16 dedicated input pins, 240 user I/Os, an internal frequency of up to 144.9 MHz, and CMOS technology with EEPROM-based configuration that holds the programmed pattern without external memory. The device supports in-system programmability via the IEEE 1149.1 (JTAG) interface, allowing field updates without removing the part from the board. It also offers programmable power-saving features on a per-macrocell basis. The MAX architecture uses Logic Array Blocks (LABs) interconnected by a programmable interconnect array (PIA). Each macrocell contains a programmable AND/OR array, a flip-flop, and feedback paths that can be routed back into the PIA, giving designers predictable, deterministic timing across all paths. The EEPROM cell technology provides non-volatile storage and 100+ erase/program cycles. Typical applications include PCI bus interface glue logic, telecom backplane address decoding, industrial motor-control state machines, legacy ISA/PC/104 bus arbitration, and DSP peripheral control. The 240-pin RQFP package provides generous I/O for parallel bus bridging and high-fanout decode functions. When designing, verify that the JTAG chain order is correctly configured and that the I/O banks are powered to the correct voltage. For new designs, consider the MAX II or MAX V families for lower power and lower cost, but retain the MAX 9000 for legacy board replacements where the footprint and timing must match exactly. This page synthesizes distributor availability, drop-in replacement candidates from the MAX 9000 family, and practical design notes that are not collected in any single manufacturer document.
EPM9560RI240-15 - 560-Macrocell MAX 9000 CPLD, 15ns, RQFP-240 | Intel
The Intel (formerly Altera) EPM9560RI240-15 is a high-density, in-system programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 560 macrocells and 772 flip-flops in a 240-pin RQFP (Power Quad Flat Pack) package. The "-15" speed grade provides a 15 ns pin-to-pin propagation delay with an internal frequency up to 145 MHz, and the device supports configurable I/O standards at 3.3 V or 5.0 V operation. It is built on a high-performance CMOS EEPROM-based process using Altera's third-generation Multiple Array MatriX (MAX) architecture. A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device that combines multiple PLA-like logic array blocks (LABs) connected through a programmable interconnect matrix (PIA). Within the broader taxonomy, the EPM9560RI240-15 sits in this hierarchy: programmable logic device -> CPLD -> EEPROM-based CPLD -> MAX architecture CPLD -> high-density (>500 macrocell) CPLD. Compared to FPGAs, CPLDs offer deterministic timing, no configuration load time, and superior pin-locking and I/O count for glue-logic, bus-interface, and state-machine applications. The EPM9560RI240-15 provides 191 user I/O pins (industrial version) with 4 dedicated inputs, JTAG-compliant in-system programmability via IEEE Std 1149.1, and a 5.0 V core with multi-voltage I/O. Each macrocell supports combinatorial or registered logic with programmable polarity, a D/T/JK/SR flip-flop, and a product-term-based local feedback path. The 240-pin RQFP package is a surface-mount gull-wing variant with a 0.500 mm terminal pitch. Typical applications include industrial automation controllers, telecommunications line cards, peripheral bus interface bridges, legacy peripheral glue logic, and consumer electronics requiring deterministic sub-25 ns logic response. Designers favor the MAX 9000 series for power-up instant-on behavior (no external boot PROM required), making it ideal for systems that must begin operation immediately after VCC is applied. When designing, ensure monotonic VCC rise per Altera's Operating Requirements; during transitions I/O pins may undershoot to -2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions. A robust decoupling network (one 0.1 uF per VCC/ground pair, plus bulk) is required to keep internal frequency up to 145 MHz. Industrial-grade operation is supported from -40 C to +85 C. This page synthesizes distributor pricing, drop-in alternatives from the same MAX 9000 family, and practical design notes not found on a single manufacturer product page, giving engineers a single decision-ready reference for sourcing, replacement, and design-in decisions.
EPM9560RI240-15N - MAX 9000 CPLD 560 Macrocell | Intel
The Intel (Altera) EPM9560RI240-15N is a MAX 9000 family EEPROM-based Complex Programmable Logic Device (CPLD) offering 560 macrocells, 772 flip-flops, and 216 user I/O pins in a 240-pin RQFP (PowerQuad/plastic quad flat pack) package, with a 15 ns pin-to-pin propagation delay and 145 MHz internal frequency. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks with a programmable interconnect matrix on a single die, allowing designers to implement custom glue logic, state machines, and bus interfaces without fabricating an ASIC. Within the semiconductor taxonomy, the MAX 9000 CPLD sits under programmable logic devices (PLDs), alongside FPGAs and simple PLDs, and is used where deterministic timing and non-volatile configuration are more important than raw gate density. The EPM9560RI240-15N is built on Altera's third-generation Multiple Array MatriX (MAX) architecture with CMOS EEPROM configuration elements, so the design is retained without an external configuration PROM. Its 560 macrocells support up to 12,000 usable gates, and the 216 I/O pins can be configured for 3.3 V or 5.0 V operation, easing mixed-voltage board integration. The -15 speed grade provides 15 ns pin-to-pin delay and 145 MHz internal operation, while the industrial temperature range supports -40 C to +85 C environments. Typical applications include legacy industrial control backplanes, telecommunications line-card glue logic, instrumentation address decoding, and bus-bridge functions in systems originally designed around the MAX 9000 family. Because the device is in-system programmable via the IEEE 1149.1 JTAG interface, field upgrades are possible without removing the part from the board. When designing with this CPLD, verify that the 5.0 V tolerant I/O banks are configured correctly for the surrounding logic levels, and provide adequate decoupling on each VCC pin. The 240-pin RQFP footprint requires careful thermal and signal-integrity planning for the high pin count. This page synthesizes distributor availability, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and migration decisions.
EPM9560RI240-20 - MAX 9000 CPLD 560 Macro 191 IO | Altera
The Altera EPM9560RI240-20 is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 560 macrocells, 191 user I/O pins, and a 20 ns pin-to-pin propagation delay, housed in a 240-pin RQFP (PowerQuad II) package. It operates from a 5.0 V supply and is specified for the industrial temperature range. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of an FPGA with the non-volatile, instant-on behavior of a PAL. CPLDs sit in the programmable logic hierarchy as CPLD -> programmable logic device (PLD) -> digital logic IC -> semiconductor. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, using CMOS EEPROM cells for configuration storage, so the device is live immediately at power-up with no external configuration memory. Key features of the EPM9560RI240-20 include 560 macrocells, 191 user I/O pins, 20 ns pin-to-pin delay, and 5.0 V in-system programmability (ISP). The EEPROM-based architecture provides non-volatile configuration, eliminating the boot PROM required by SRAM-based FPGAs. The 240-pin RQFP package with exposed pad supports high I/O count in a surface-mount footprint. The MAX 9000 architecture uses a hierarchical routing scheme with logic array blocks (LABs) feeding a central interconnect array, giving predictable timing independent of routing. This deterministic timing is a key advantage over FPGA architectures for glue-logic, bus-interface, and state-machine designs where worst-case delay must be guaranteed. Typical applications include legacy industrial control boards, bus bridging and address decoding, telecommunications line-card glue logic, test and measurement instrumentation, and replacement of discrete 74-series logic. The 5.0 V I/O interface is directly compatible with TTL and 5 V CMOS logic, simplifying interfacing to legacy peripherals. When designing with this device, verify that the 240-pin RQFP land pattern matches the PowerQuad II footprint and provide adequate thermal relief on the exposed pad. Because the part is a mature MAX 9000 device, confirm lifecycle status and availability before committing to new production. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for the EPM9560RI240-20.
EPM9560RI240-20C - MAX 9000 560-Macrocell CPLD, 240-RQFP | Altera
The Altera EPM9560RI240-20C is a high-density, in-system-programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 12,000 usable gates, 560 macrocells, and 191 user I/Os in a 240-pin RQFP package. It operates from a 5 V supply and is built on Altera's third-generation Multiple Array Matrix (MAX) architecture using advanced EEPROM-based CMOS technology, with a maximum propagation delay of approximately 20 ns (the -20 speed grade) and a typical internal operating frequency of 100 MHz. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the instant-on, deterministic timing of traditional PAL/GAL devices with much higher logic density. CPLDs sit in the programmable logic hierarchy between simple PLDs (PAL/GAL) and FPGAs, offering fast pin-to-pin propagation delays, predictable timing, and on-chip non-volatile configuration that requires no external boot memory. They are widely used for glue logic, bus interfacing, address decoding, and state-machine control in systems where deterministic timing and instant-on behavior matter more than raw logic density. Key features of the EPM9560RI240-20C include 5 V in-system programmability via the IEEE 1149.1 JTAG boundary-scan test (BST) interface, support for 3.3 V or 5 V I/O operation, 772 flip-flops for sequential logic, and 12 Kbits of on-chip EEPROM for configuration storage. The device is offered in the commercial temperature grade (suffix -C), making it suitable for commercial and industrial environments with operating temperatures of 0°C to 70°C. Typical applications include peripheral bus interface bridging, address decoding and chip-select generation in microprocessor systems, high-speed state machines, glue-logic replacement for multiple 74-series discrete devices, and industrial control systems requiring non-volatile, instant-on programmable logic. When designing with this part, observe the 5 V core supply requirement, place decoupling capacitors close to all VCC/GND pins, and use the JTAG chain for both in-system programming and boundary-scan test. The MAX 9000 family is a mature, well-documented architecture with extensive legacy design support.
EPM9560RI240-20N - MAX 9000 CPLD, 560 Macro, 191 I/O | Intel
The Intel EPM9560RI240-20N is a high-density, 5.0-V in-system programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 560 macrocells and 191 user I/Os in a 240-pin BGA-style power-enhanced package. It is built on a third-generation Multiple Array MatriX (MAX) architecture that combines the density of FPGAs with the predictability and non-volatility of classic PLDs, and is fabricated with a CMOS EEPROM process that supports 5.0-V in-system programmability through the IEEE 1149.1 JTAG interface. The device delivers an internal frequency up to 145 MHz with a pin-to-pin propagation delay of 11.4 ns, making it suitable for high-performance glue logic, bus interfacing, and state-machine heavy designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that uses on-chip EEPROM or flash memory to store the configuration. CPLDs sit in the programmable logic hierarchy between simple PLDs (PALs/GALs) and FPGAs: they offer deterministic timing (fixed propagation delay), instant-on operation (no external boot memory), high drive strength, and a Logic Array Block (LAB) structure connected by a programmable interconnect matrix (PIA). The MAX architecture extends classic CPLD concepts with finer-grained logic elements (macrocells), more flexible I/O, and higher usable density, and the 9000 series is positioned as the high-density tier of that family tree. Key features of the EPM9560RI240-20N include 560 dedicated macrocells (12 Logic Array Blocks), a maximum internal operating frequency of 145 MHz, 11.4 ns propagation delay through the PIA, multiVolt I/O supporting 5.0-V and 3.3-V mixed-voltage interfaces, and a 5.0-V core supply. The die supports user-configurable I/O standards, in-system programmability via JTAG, and is supported by the legacy Altera MAX+PLUS II and Quartus II design environments. Device power is estimated using Altera's PowerPlay power estimation methodology integrated into those tools. The MAX architecture uses each macrocell to implement a sum-of-products combinatorial function plus an optional flip-flop, with fast feedback paths to the PIA. Global routing is deterministic, which means designers can compute worst-case timing paths analytically - useful for asynchronous bus bridges, interrupt controllers, and other latency-critical glue logic. The 5.0-V tolerant I/O and strong drive capability allow direct interface to TTL/CMOS buses without external transceivers. Typical applications include high-performance bus interfacing (PCI, VME, ISA bridges), address decoding and wait-state generation in microprocessor systems, state-machine controllers for industrial and telecom equipment, glue logic for ASIC/FPGA-based designs, and high-pin-count glue logic on VME/cPCI backplanes. The 191 user I/O pins enable direct fan-out to wide memory buses and peripheral banks without additional buffering. When designing with this device, allocate global clocks carefully - the MAX 9000 has a finite number of global clock pins and LAB-local clock resources. Use the MAX+PLUS II fitter report or Quartus compilation report to verify pin assignments and resource utilization, and respect the 5.0-V VCCIO requirements if mixing with 3.3-V peripherals through level-shifting I/O standards. Decoupling bulk 0.1 uF and 10 uF capacitors should be placed as close as possible to every VCC/VCCIO pin to meet in-system programming noise margins. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, including the same-family EPM9560 speed/pinout variants that share the same 240-pin package footprint.
EPM9560RI304 - MAX 9000 CPLD 560 Macrocell 304-Pin RQFP | Altera
The Altera EPM9560RI304 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 560 macrocells with a 20 ns pin-to-pin propagation delay, housed in a 304-pin BFQFP/RQFP package. It is a 5.0 V EEPROM-based programmable logic device built on third-generation Multiple Array MatriX (MAX) architecture with in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of a field-programmable gate array with the non-volatile, instant-on characteristics of a PAL/GAL. CPLDs sit between simple programmable logic devices and FPGAs in the programmable logic hierarchy: PLD -> CPLD -> FPGA -> programmable logic semiconductor. The MAX 9000 family uses EEPROM configuration cells, so the device retains its configuration without an external boot PROM and is operational immediately after power-up. The EPM9560RI304 provides 560 macrocells, 12,000 usable gates, and 216 maximum user I/O pins, making it suitable for glue logic consolidation, bus interface bridging, and state-machine implementations that exceed the capacity of smaller MAX 7000 devices. The 20 ns propagation delay supports system clock rates in the 50 MHz class for combinatorial paths, while the 304-pin RQFP package provides the I/O count needed for wide bus interfaces. The MAX 9000 architecture is based on Logic Array Blocks (LABs) interconnected by a fast Programmable Interconnect Array (PIA), delivering deterministic, predictable timing without the place-and-route timing closure iterations typical of SRAM-based FPGAs. The 5.0 V core and I/O simplify interfacing to legacy 5 V TTL/CMOS logic, which is a key advantage in industrial and telecom equipment retrofits. Typical applications include industrial control backplanes, telecom line-card glue logic, legacy system maintenance, test equipment, and military/aerospace programs where 5 V logic and non-volatile configuration are mandatory. The industrial temperature grade (-40C to +85C) supports deployment in factory-floor and outdoor equipment. When designing with the EPM9560RI304, note that the device is configured via the JTAG interface and requires a 5.0 V supply with careful decoupling on every VCC pin. Because the part is a legacy MAX 9000 device, designers should confirm lifecycle status and consider MAX II or MAX V migration for new designs. This page synthesizes distributor availability, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing a single reference for engineers maintaining or sourcing the EPM9560RI304.
EPM9560RI304-15 - 560-Macrocell MAX 9000 CPLD | Intel/Altera | 15ns
The Altera (now Intel) EPM9560RI304-15 is a high-performance CMOS EEPROM-based programmable logic device (PLD) built on the third-generation Multiple Array MatriX (MAX) architecture, housed in a 304-pin RQFP/HFQFP package. It integrates 560 macrocells, 772 flip-flops, and 212 user I/Os, with a propagation delay of 11.4 ns and a maximum internal clock frequency of 145 MHz, making it one of the highest-density members of the MAX 9000 family. A CPLD (Complex Programmable Logic Device) is a non-volatile, reprogrammable integrated circuit that combines the deterministic timing of classic PLDs with much higher logic density, suitable for wide glue-logic, bus-interface, and state-machine functions. The MAX 9000 family sits in the hierarchy of programmable logic devices (PLD) -> CPLD -> programmable logic -> semiconductor, and is fabricated on a 5.0-V EEPROM process that supports in-system programmability (ISP) via JTAG. Key features of the EPM9560RI304-15 include 212 user I/Os configurable for 3.3 V or 5 V operation, a 4.5 V to 5.5 V supply range, an industrial temperature grade, and a propagation delay of 11.4 ns corresponding to the -15 speed grade. The Logic Array Blocks (LABs) and FastTrack interconnect deliver predictable, deterministic pin-to-pin timing, which is critical for asynchronous bus arbitration, address decoding, and clock-generation logic. The device is implemented in 0.5 µm CMOS EEPROM technology with on-chip charge pumps for in-system programming, eliminating the need for external boot memory. The MAX architecture uses a uniform interconnect that lets every macrocell drive every I/O pin, simplifying place-and-route while preserving fixed, application-independent timing. Typical applications include 32-bit and 64-bit bus decoding, peripheral glue logic in telecom and industrial controllers, address mapping and chip-select generation, and high-density state machines. The 304-pin package provides ample I/O for parallel interfaces, while the 560-macrocell capacity supports logic equivalent to several thousand gates. When designing with this part, ensure that the JTAG chain is correctly terminated (TCK pulled low, TMS pulled high at reset) and that I/O banks are powered within the 3.3 V or 5 V rail specifications. Decoupling of each VCC pin with 0.1 µF ceramics placed within 5 mm of the pin is essential for reliable ISP operation. This page consolidates distributor pricing, drop-in same-package variants, and practical design notes that complement the manufacturer datasheet.
EPM9560RI304-15N - 560-Macrocell MAX 9000 CPLD, 15ns, RQ304 | Altera
The Altera EPM9560RI304-15N is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 560 macrocells and 772 flip-flops in a 304-pin RQFP package. It features a maximum internal frequency of 145 MHz, a propagation delay of 15 ns through the worst-case interconnect, and supports configurable I/O operation at 3.3 V or 5.0 V. The device is implemented in 5.0-V in-system programmable EEPROM technology built on the third-generation Multiple Array MatriX (MAX) architecture. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that sits between small-scale discrete logic (74-series gates) and large FPGAs in the programmable logic hierarchy. CPLDs use a classic AND-OR programmable plane feeding a fixed number of macrocells, giving them deterministic, fast, pin-to-pin propagation delays and instant-on behavior from non-volatile EEPROM configuration memory. They are commonly used for glue logic, bus interface bridging, address decoding, and state-machine control where predictable timing matters more than raw logic density. Key features of the EPM9560RI304-15N include 16 Logic Array Blocks (LABs) interconnected by the Programmable Interconnect Array (PIA), 216 user I/O pins, JTAG-based IEEE 1532 in-system programmability, and pin-compatibility across the MAX 9000 family. The RQFP-304 (also referenced as HFQFP-304 in distributor data) provides a 1.27 mm gull-wing pitch for surface-mount assembly. Per the Altera MAX 9000 datasheet, the device supports multi-volt I/O and operates across the commercial 0 C to 70 C range. Architecturally, the EPM9560RI304-15N combines the predictable timing of EEPROM-based macrocells with the density and routability of a structured interconnect, making it well suited to mid-complexity logic replacement (hundreds to a few thousand gates) and peripheral expansion. The 15 ns speed grade is the mid-tier timing bin, balanced between pin-to-pin delay and static power consumption. Designers use MAX 9000 CPLDs for I/O expansion, bus decoding, address mapping, and as glue logic between microprocessors, microcontrollers, and FPGAs. Typical applications include legacy peripheral replacement, glue logic in industrial controllers, bus address decoding for PowerPC/MIPS/ARM boards, JTAG-controlled I/O expansion, and rapid prototyping of state machines. The combination of non-volatile instant-on configuration, JTAG programming, and deterministic timing also makes it attractive in safety-related industrial equipment where predictable behavior at power-on is required. When designing with the EPM9560RI304-15N, ensure the supply voltage and I/O bank voltages match the JTAG chain order and other boundary-scan devices. Decoupling follows standard high-pin-count CMOS practice: 0.1 uF ceramic bypass on every VCC/VCCIO pin pair and a single bulk 10-47 uF tantalum or ceramic near the package. Because the device is 5-V core with multi-volt I/O, level translation is handled on-chip but input over-voltage on 3.3 V banks must be respected. The Altera MAX+PLUS II or Quartus MAX device support file is required for synthesis. This page synthesizes distributor pricing, MAX 9000 family pin-compatible alternatives, and practical CPLD design guidance not collected in a single datasheet excerpt.
EPM9560RI304-20 - 560 Macrocell MAX 9000 CPLD, 20ns, RQFP-304 | Intel
The Intel (Altera) EPM9560RI304-20 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, delivering 560 macrocells in a 304-pin RQFP (Plastic Quad Flat Pack) package with a 20 ns pin-to-pin propagation delay. It is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, providing 5.0 V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single chip with a programmable interconnect fabric. It sits in the programmable logic hierarchy below FPGAs (in density) but above simple SPLDs (in integration), belonging to the broader semiconductor category of programmable logic devices. CPLDs are favored for glue-logic, bus interfacing, and state-machine implementation because they offer deterministic timing, instant-on (no configuration load time), and non-volatile storage of the bitstream. Key features of the EPM9560RI304-20 include 560 macrocells, 16 logic array blocks (LABs), a maximum of 212 user I/O pins, programmable interconnect, and 5 V in-system programmability via JTAG (IEEE 1149.1). The MAX 9000 family supports the IEEE 1149.1 boundary-scan standard for board-level testability. The device is fabricated on a 5.0 V CMOS EEPROM process, allowing the configuration to be retained without external memory. The 304-pin RQFP package provides a high I/O count for bus-intensive applications. The MAX architecture uses Logic Array Blocks (LABs) of 16 macrocells each, with a global programmable interconnect array (PIA) routing signals between LABs and I/O pins. Each macrocell contains a programmable AND/OR array with a configurable flip-flop, supporting both combinatorial and registered logic. The EEPROM cell technology enables 100+ in-system reprogramming cycles, allowing field upgrades without removing the device from the board. Typical applications include high-speed glue logic, bus interfacing (PCI, ISA, VME), state-machine controllers, peripheral interface bridges, and digital signal conditioning. The 5 V tolerant I/Os make it suitable for industrial and legacy telecom systems where 3.3 V logic is not required. The instant-on behavior (no boot PROM needed) is ideal for safety-critical and deterministic-latency applications. When designing with the EPM9560RI304-20, observe the maximum I/O pin count of 212 and ensure the JTAG chain follows the IEEE 1149.1 topology for board-level testability. Power supply decoupling requires 0.1 uF ceramic capacitors placed close to each VCC pin. The device operates from a single 5.0 V supply, simplifying power-tree design compared to multi-rail FPGAs. This page synthesizes distributor pricing, drop-in MAX 9000 alternatives, and design guidance not found in the standalone manufacturer datasheet, helping engineers select and source the EPM9560RI304-20 with confidence.
EPM9560RI304-20C - 560-Macrocell MAX 9000 CPLD, 5V, 304-Pin RQFP | Altera
The Altera EPM9560RI304-20C is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, featuring 560 macrocells, 212 user I/O pins, and a 100 MHz maximum internal clock frequency in a 304-pin RQFP (Plastic Quad Flat Pack) surface-mount package. It provides 12,000 usable gates with 23.6 ns pin-to-pin propagation delay, operates from a single 5.0 V supply, and supports in-system programmability via the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL/GAL-style macrocell arrays on a single die, connected by a programmable interconnect matrix (the Multiple Array MatriX, or MAX, architecture used here). Unlike FPGAs, which use RAM-based lookup tables and require external boot memory, CPLDs retain their configuration in on-chip EEPROM and provide deterministic, glitch-free propagation delays. MAX 9000 sits in Altera's taxonomy as a high-density 5V legacy CPLD, between MAX 7000 (mid-density 5V) and FLEX 10K (early SRAM-based FPGA). Key features include third-generation MAX architecture for predictable timing, 5.0 V in-system programmability through JTAG (IEEE 1149.1), 16 logic array blocks, 36 macrocells per LAB, fast parallel expansion across multiple devices, and pin-compatible speed grades (-20, -15, -10) within the EPM9560 family. The 304-pin RQFP provides the maximum I/O count (212) for the EPM9560 die, allowing it to replace multiple discrete logic ICs in glue-logic, bus-interface, and state-machine roles. The EPM9560RI304-20C uses CMOS EEPROM process technology with a multi-array matrix interconnect that distributes signals across 16 LABs in a predictable, deterministic-timing fabric. Designers can synthesize state machines, decoders, and bus interfaces using Altera/Intel Quartus II (legacy MAX+PLUS II) software, then program the device in-system through the JTAG pins without removing it from the board. This makes it well-suited for long-life industrial equipment where field upgrades are rare but reliability is critical. Typical applications include industrial control glue logic, telecommunications bus interfaces, ASIC prototyping, peripheral controllers, and legacy 5V system designs. It is also used as a bus arbiter or address decoder where deterministic 23.6 ns propagation delay and 5V tolerance are required. When designing with the EPM9560RI304-20C, ensure the JTAG chain (TCK, TMS, TDI, TDO) is properly terminated and that unused I/O pins are left floating or grounded per the MAX 9000 datasheet to minimize inrush during ISP. Note that newer 3.3V-only designs should migrate to MAX II or MAX V families instead. This page synthesizes distributor pricing, in-package same-family drop-in alternatives, and practical JTAG/5V design notes that are not assembled in any single manufacturer or distributor page.
EPM9560RI304-20N - 560-Macrocell MAX 9000 CPLD, 20ns, 5V | Intel
The Intel (Altera) EPM9560RI304-20N is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, delivering 560 macrocells, 12,000 usable gates, and a 20 ns pin-to-pin propagation delay in a 304-pin RQFP (Plastic Quad Flat Pack) package. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, it integrates multiple Logic Array Blocks (LABs) interconnected by the programmable FastTrack interconnect, with each macrocell containing a programmable AND/OR array plus a configurable flip-flop for sequential or combinational logic implementation. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that retains configuration without external memory and offers deterministic, near-zero propagation delay suitable for glue logic, bus interfacing, address decoding, and state-machine replacement. Within the broader programmable logic hierarchy, CPLDs sit between simple SPLDs (PAL/GAL) and high-density FPGAs, offering predictable timing, instant-on operation, and high I/O counts that FPGAs in the same cost class cannot match. Key features include 5.0 V in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface, 304 user I/O pins, 212 inputs with fast input logic, a 100 MHz internal performance grade, and CMOS-compatible I/O. The EPM9560RI304-20N variant carries the -20 speed grade (20 ns tPD), making it the slowest but most cost-optimized option in the EPM9560RI304 family versus the -15 and -10 grades. Architecturally, the device partitions logic across LABs of 16 macrocells each, with each macrocell supporting product-term allocation, D/T/JK flip-flop configuration, and global/array clock selection. The FastTrack continuous routing array provides uniform, predictable interconnect delay regardless of placement - a hallmark advantage of CPLDs versus FPGAs. Typical applications include high-speed bus decoding, peripheral interfacing, glue logic in telecom and industrial control boards, address/data multiplexing, and replacement of multiple discrete SSI/MSI logic packages. Designers also use the EPM9560RI304-20N for system-level power-on reset sequencing and interrupt prioritization in legacy 5 V designs. When designing with this part, note that the 304-pin RQFP package requires a generous PCB land pattern and careful thermal management. Quartus II (legacy) or MAX+PLUS II software is required for design entry, fitting, and programming via the JTAG port. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical 5 V design notes not found in the manufacturer datasheet alone.