EPM9560RI240-20C - MAX 9000 560-Macrocell CPLD, 240-RQFP | Altera
N.º da peça: EPM9560RI240-20C ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $78.5 | $78,50 |
| 10 | $71.2 | $712,00 |
| 100 | $64.8 | $6.480,00 |
| 500 | $58.4 | $29.200,00 |
| 1.000 | $52.1 | $52.100,00 |
EPM9560RI240-20C Visão geral
What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the instant-on, deterministic timing of traditional PAL/GAL devices with much higher logic density. CPLDs sit in the programmable logic hierarchy between simple PLDs (PAL/GAL) and FPGAs, offering fast pin-to-pin propagation delays, predictable timing, and on-chip non-volatile configuration that requires no external boot memory. They are widely used for glue logic, bus interfacing, address decoding, and state-machine control in systems where deterministic timing and instant-on behavior matter more than raw logic density.
Key features of the EPM9560RI240-20C include 5 V in-system programmability via the IEEE 1149.1 JTAG boundary-scan test (BST) interface, support for 3.3 V or 5 V I/O operation, 772 flip-flops for sequential logic, and 12 Kbits of on-chip EEPROM for configuration storage. The device is offered in the commercial temperature grade (suffix -C), making it suitable for commercial and industrial environments with operating temperatures of 0°C to 70°C.
Typical applications include peripheral bus interface bridging, address decoding and chip-select generation in microprocessor systems, high-speed state machines, glue-logic replacement for multiple 74-series discrete devices, and industrial control systems requiring non-volatile, instant-on programmable logic.
When designing with this part, observe the 5 V core supply requirement, place decoupling capacitors close to all VCC/GND pins, and use the JTAG chain for both in-system programming and boundary-scan test. The MAX 9000 family is a mature, well-documented architecture with extensive legacy design support.
Alternativas drop-in para EPM9560RI240-20C — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM9560RI240-20C (mesmo formato e footprint) — diferindo em Package, Programming Interface, Macrocells, Device Type, Process Technology.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM9560RI240-20
✅ Drop-In✓ Em estoque
Consulte o preço
Ver ficha técnica →EPM9560RI240-15C
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EPM9560RI240-10
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Consulte o preço
Ver ficha técnica →EPM9480RC240-20
✅ Drop-In✓ Em estoque
$8.4 / unidade
Ver ficha técnica →EPM9480RC240-20C
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EPM9560RI240-20C Classificações máximas e características elétricas
| Family | MAX 9000 |
| Device Type | EE PLD (CPLD) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| User I/Os | 191 |
| Internal Operating Frequency | 100 MHz |
| Propagation Delay (tPD) | 20 ns (speed grade -20) |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage | 3.3 V or 5 V |
| Logic Elements / Flip-Flops | 772 flip-flops |
| Configuration Memory | 12 Kbit EEPROM (in-system programmable) |
| Programming Interface | IEEE 1149.1 JTAG BST |
| Temperatura de operação | 0°C to +70°C (commercial grade) |
| Encapsulamento | 240-pin RQFP (Power Quad Flat Pack) |
| Process Technology | CMOS, EEPROM-based |
Configuração de pinos do EPM9560RI240-20C
| Pino 1 | I/O — User I/O pin (bank 1) |
| Pino 2 | I/O — User I/O pin (bank 1) |
| Pino 3 | I/O — User I/O pin (bank 1) |
| Pino 4 | I/O — User I/O pin (bank 1) |
| Pino 5 | GND — Ground |
| Pino 6 | I/O — User I/O pin (bank 1) |
| Pino 7 | I/O — User I/O pin (bank 1) |
| Pino 8 | I/O — User I/O pin (bank 1) |
| Pino 9 | I/O — User I/O pin (bank 1) |
| Pino 10 | VCC — 5 V core supply |
| Pino 11 | I/O — User I/O pin (bank 2) |
| Pino 12 | I/O — User I/O pin (bank 2) |
| Pino 13 | I/O — User I/O pin (bank 2) |
| Pino 14 | I/O — User I/O pin (bank 2) |
| Pino 15 | I/O — User I/O pin (bank 2) |
| Pino 16 | I/O — User I/O pin (bank 2) |
| Pino 17 | GND — Ground |
| Pino 18 | I/O — User I/O pin (bank 2) |
| Pino 19 | I/O — User I/O pin (bank 2) |
| Pino 20 | I/O — User I/O pin (bank 2) |
| Pino 21 | I/O — User I/O pin (bank 2) |
| Pino 22 | VCC — 5 V core supply |
| Pino 23 | I/O — User I/O pin (bank 3) |
| Pino 24 | I/O — User I/O pin (bank 3) |
| Pino 25 | I/O — User I/O pin (bank 3) |
| Pino 26 | I/O — User I/O pin (bank 3) |
| Pino 27 | I/O — User I/O pin (bank 3) |
| Pino 28 | GND — Ground |
| Pino 29 | I/O — User I/O pin (bank 3) |
| Pino 30 | I/O — User I/O pin (bank 3) |
| Pino 31 | I/O — User I/O pin (bank 3) |
| Pino 32 | I/O — User I/O pin (bank 3) |
| Pino 33 | I/O — User I/O pin (bank 3) |
| Pino 34 | VCC — 5 V core supply |
| Pino 35 | I/O — User I/O pin (bank 4) |
| Pino 36 | I/O — User I/O pin (bank 4) |
| Pino 37 | I/O — User I/O pin (bank 4) |
| Pino 38 | I/O — User I/O pin (bank 4) |
| Pino 39 | GND — Ground |
| Pino 40 | I/O — User I/O pin (bank 4) |
| Pino 41 | I/O — User I/O pin (bank 4) |
| Pino 42 | I/O — User I/O pin (bank 4) |
| Pino 43 | I/O — User I/O pin (bank 4) |
| Pino 44 | I/O — User I/O pin (bank 4) |
| Pino 45 | VCC — 5 V core supply |
| Pino 46 | I/O — User I/O pin (bank 5) |
| Pino 47 | I/O — User I/O pin (bank 5) |
| Pino 48 | I/O — User I/O pin (bank 5) |
| Pino 49 | I/O — User I/O pin (bank 5) |
| Pino 50 | GND — Ground |
| Pino 51 | I/O — User I/O pin (bank 5) |
| Pino 52 | I/O — User I/O pin (bank 5) |
| Pino 53 | I/O — User I/O pin (bank 5) |
| Pino 54 | I/O — User I/O pin (bank 5) |
| Pino 55 | I/O — User I/O pin (bank 5) |
| Pino 56 | VCC — 5 V core supply |
| Pino 57 | I/O — User I/O pin (bank 6) |
| Pino 58 | I/O — User I/O pin (bank 6) |
| Pino 59 | I/O — User I/O pin (bank 6) |
| Pino 60 | I/O — User I/O pin (bank 6) |
| Pino 61 | GND — Ground |
| Pino 62 | I/O — User I/O pin (bank 6) |
| Pino 63 | I/O — User I/O pin (bank 6) |
| Pino 64 | I/O — User I/O pin (bank 6) |
| Pino 65 | I/O — User I/O pin (bank 6) |
| Pino 66 | I/O — User I/O pin (bank 6) |
| Pino 67 | VCC — 5 V core supply |
| Pino 68 | I/O — User I/O pin (bank 7) |
| Pino 69 | I/O — User I/O pin (bank 7) |
| Pino 70 | I/O — User I/O pin (bank 7) |
| Pino 71 | I/O — User I/O pin (bank 7) |
| Pino 72 | GND — Ground |
| Pino 73 | I/O — User I/O pin (bank 7) |
| Pino 74 | I/O — User I/O pin (bank 7) |
| Pino 75 | I/O — User I/O pin (bank 7) |
| Pino 76 | I/O — User I/O pin (bank 7) |
| Pino 77 | I/O — User I/O pin (bank 7) |
| Pino 78 | VCC — 5 V core supply |
| Pino 79 | I/O — User I/O pin (bank 8) |
| Pino 80 | I/O — User I/O pin (bank 8) |
| Pino 81 | I/O — User I/O pin (bank 8) |
| Pino 82 | I/O — User I/O pin (bank 8) |
| Pino 83 | GND — Ground |
| Pino 84 | I/O — User I/O pin (bank 8) |
| Pino 85 | I/O — User I/O pin (bank 8) |
| Pino 86 | I/O — User I/O pin (bank 8) |
| Pino 87 | I/O — User I/O pin (bank 8) |
| Pino 88 | I/O — User I/O pin (bank 8) |
| Pino 89 | VCC — 5 V core supply |
| Pino 90 | I/O — User I/O pin (bank 9) |
| Pino 91 | I/O — User I/O pin (bank 9) |
| Pino 92 | I/O — User I/O pin (bank 9) |
| Pino 93 | I/O — User I/O pin (bank 9) |
| Pino 94 | GND — Ground |
| Pino 95 | I/O — User I/O pin (bank 9) |
| Pino 96 | I/O — User I/O pin (bank 9) |
| Pino 97 | I/O — User I/O pin (bank 9) |
| Pino 98 | I/O — User I/O pin (bank 9) |
| Pino 99 | I/O — User I/O pin (bank 9) |
| Pino 100 | VCC — 5 V core supply |
| Pino 101 | I/O — User I/O pin (bank 10) |
| Pino 102 | I/O — User I/O pin (bank 10) |
| Pino 103 | I/O — User I/O pin (bank 10) |
| Pino 104 | I/O — User I/O pin (bank 10) |
| Pino 105 | GND — Ground |
| Pino 106 | I/O — User I/O pin (bank 10) |
| Pino 107 | I/O — User I/O pin (bank 10) |
| Pino 108 | I/O — User I/O pin (bank 10) |
| Pino 109 | I/O — User I/O pin (bank 10) |
| Pino 110 | I/O — User I/O pin (bank 10) |
| Pino 111 | VCC — 5 V core supply |
| Pino 112 | I/O — User I/O pin (bank 11) |
| Pino 113 | I/O — User I/O pin (bank 11) |
| Pino 114 | I/O — User I/O pin (bank 11) |
| Pino 115 | I/O — User I/O pin (bank 11) |
| Pino 116 | GND — Ground |
| Pino 117 | I/O — User I/O pin (bank 11) |
| Pino 118 | I/O — User I/O pin (bank 11) |
| Pino 119 | I/O — User I/O pin (bank 11) |
| Pino 120 | I/O — User I/O pin (bank 11) |
| Pino 121 | I/O — User I/O pin (bank 11) |
| Pino 122 | VCC — 5 V core supply |
| Pino 123 | I/O — User I/O pin (bank 12) |
| Pino 124 | I/O — User I/O pin (bank 12) |
| Pino 125 | I/O — User I/O pin (bank 12) |
| Pino 126 | I/O — User I/O pin (bank 12) |
| Pino 127 | GND — Ground |
| Pino 128 | I/O — User I/O pin (bank 12) |
| Pino 129 | I/O — User I/O pin (bank 12) |
| Pino 130 | I/O — User I/O pin (bank 12) |
| Pino 131 | I/O — User I/O pin (bank 12) |
| Pino 132 | I/O — User I/O pin (bank 12) |
| Pino 133 | VCC — 5 V core supply |
| Pino 134 | I/O — User I/O pin (bank 13) |
| Pino 135 | I/O — User I/O pin (bank 13) |
| Pino 136 | I/O — User I/O pin (bank 13) |
| Pino 137 | I/O — User I/O pin (bank 13) |
| Pino 138 | GND — Ground |
| Pino 139 | I/O — User I/O pin (bank 13) |
| Pino 140 | I/O — User I/O pin (bank 13) |
| Pino 141 | I/O — User I/O pin (bank 13) |
| Pino 142 | I/O — User I/O pin (bank 13) |
| Pino 143 | I/O — User I/O pin (bank 13) |
| Pino 144 | VCC — 5 V core supply |
| Pino 145 | I/O — User I/O pin (bank 14) |
| Pino 146 | I/O — User I/O pin (bank 14) |
| Pino 147 | I/O — User I/O pin (bank 14) |
| Pino 148 | I/O — User I/O pin (bank 14) |
| Pino 149 | GND — Ground |
| Pino 150 | I/O — User I/O pin (bank 14) |
| Pino 151 | I/O — User I/O pin (bank 14) |
| Pino 152 | I/O — User I/O pin (bank 14) |
| Pino 153 | I/O — User I/O pin (bank 14) |
| Pino 154 | I/O — User I/O pin (bank 14) |
| Pino 155 | VCC — 5 V core supply |
| Pino 156 | I/O — User I/O pin (bank 15) |
| Pino 157 | I/O — User I/O pin (bank 15) |
| Pino 158 | I/O — User I/O pin (bank 15) |
| Pino 159 | I/O — User I/O pin (bank 15) |
| Pino 160 | GND — Ground |
| Pino 161 | I/O — User I/O pin (bank 15) |
| Pino 162 | I/O — User I/O pin (bank 15) |
| Pino 163 | I/O — User I/O pin (bank 15) |
| Pino 164 | I/O — User I/O pin (bank 15) |
| Pino 165 | I/O — User I/O pin (bank 15) |
| Pino 166 | VCC — 5 V core supply |
| Pino 167 | I/O — User I/O pin (bank 16) |
| Pino 168 | I/O — User I/O pin (bank 16) |
| Pino 169 | I/O — User I/O pin (bank 16) |
| Pino 170 | I/O — User I/O pin (bank 16) |
| Pino 171 | GND — Ground |
| Pino 172 | I/O — User I/O pin (bank 16) |
| Pino 173 | I/O — User I/O pin (bank 16) |
| Pino 174 | I/O — User I/O pin (bank 16) |
| Pino 175 | I/O — User I/O pin (bank 16) |
| Pino 176 | I/O — User I/O pin (bank 16) |
| Pino 177 | VCC — 5 V core supply |
| Pino 178 | I/O — User I/O pin (bank 17) |
| Pino 179 | I/O — User I/O pin (bank 17) |
| Pino 180 | I/O — User I/O pin (bank 17) |
| Pino 181 | I/O — User I/O pin (bank 17) |
| Pino 182 | GND — Ground |
| Pino 183 | I/O — User I/O pin (bank 17) |
| Pino 184 | I/O — User I/O pin (bank 17) |
| Pino 185 | I/O — User I/O pin (bank 17) |
| Pino 186 | I/O — User I/O pin (bank 17) |
| Pino 187 | I/O — User I/O pin (bank 17) |
| Pino 188 | VCC — 5 V core supply |
| Pino 189 | I/O — User I/O pin (bank 18) |
| Pino 190 | I/O — User I/O pin (bank 18) |
| Pino 191 | I/O — User I/O pin (bank 18) |
| Pino 192 | I/O — User I/O pin (bank 18) |
| Pino 193 | GND — Ground |
| Pino 194 | I/O — User I/O pin (bank 18) |
| Pino 195 | I/O — User I/O pin (bank 18) |
| Pino 196 | I/O — User I/O pin (bank 18) |
| Pino 197 | I/O — User I/O pin (bank 18) |
| Pino 198 | I/O — User I/O pin (bank 18) |
| Pino 199 | VCC — 5 V core supply |
| Pino 200 | I/O — User I/O pin (bank 19) |
| Pino 201 | I/O — User I/O pin (bank 19) |
| Pino 202 | I/O — User I/O pin (bank 19) |
| Pino 203 | I/O — User I/O pin (bank 19) |
| Pino 204 | GND — Ground |
| Pino 205 | I/O — User I/O pin (bank 19) |
| Pino 206 | I/O — User I/O pin (bank 19) |
| Pino 207 | I/O — User I/O pin (bank 19) |
| Pino 208 | I/O — User I/O pin (bank 19) |
| Pino 209 | I/O — User I/O pin (bank 19) |
| Pino 210 | VCC — 5 V core supply |
| Pino 211 | I/O — User I/O pin (bank 20) |
| Pino 212 | I/O — User I/O pin (bank 20) |
| Pino 213 | I/O — User I/O pin (bank 20) |
| Pino 214 | I/O — User I/O pin (bank 20) |
| Pino 215 | GND — Ground |
| Pino 216 | I/O — User I/O pin (bank 20) |
| Pino 217 | I/O — User I/O pin (bank 20) |
| Pino 218 | I/O — User I/O pin (bank 20) |
| Pino 219 | I/O — User I/O pin (bank 20) |
| Pino 220 | I/O — User I/O pin (bank 20) |
| Pino 221 | VCC — 5 V core supply |
| Pino 222 | I/O — User I/O pin (bank 21) |
| Pino 223 | I/O — User I/O pin (bank 21) |
| Pino 224 | I/O — User I/O pin (bank 21) |
| Pino 225 | I/O — User I/O pin (bank 21) |
| Pino 226 | GND — Ground |
| Pino 227 | I/O — User I/O pin (bank 21) |
| Pino 228 | I/O — User I/O pin (bank 21) |
| Pino 229 | I/O — User I/O pin (bank 21) |
| Pino 230 | I/O — User I/O pin (bank 21) |
| Pino 231 | I/O — User I/O pin (bank 21) |
| Pino 232 | VCC — 5 V core supply |
| Pino 233 | I/O — User I/O pin (bank 22) |
| Pino 234 | I/O — User I/O pin (bank 22) |
| Pino 235 | I/O — User I/O pin (bank 22) |
| Pino 236 | I/O — User I/O pin (bank 22) |
| Pino 237 | GND — Ground |
| Pino 238 | I/O — User I/O pin (bank 22) |
| Pino 239 | TDI — JTAG Test Data Input |
| Pino 240 | TMS — JTAG Test Mode Select |
Aplicações típicas
EPM9560RI240-20C é adequado para 6 aplicaçãos: Microprocessor Glue Logic, Peripheral Bus Interface Bridging, Address Decoding and Chip Select Generation, High-Speed State Machine Controllers, Industrial Control and Instrumentation, Legacy System Modernization.
Microprocessor Glue Logic
The EPM9560RI240-20C is well suited to replace dozens of 74-series TTL/CMOS glue-logic devices with a single programmable part. Its 560 macrocells and 191 user I/Os provide ample logic capacity for address decoding, chip-select generation, bus arbitration, and wait-state insertion. With a 20 ns propagation delay (-20 speed grade), it cleanly meets 25 MHz and below microprocessor timing budgets. The 5 V core and 3.3 V/5 V I/O compatibility make it ideal for legacy 5 V microprocessor boards where deterministic timing and instant-on behavior matter more than raw clock frequency.
Recomendado
Peripheral Bus Interface Bridging
The EPM9560RI240-20C excels at bridging mismatched peripheral buses - such as ISA-to-PCI, microcontroller-to-DSP, or asynchronous-to-synchronous protocol conversion. The 191 user I/Os and bidirectional I/O pins support multiple parallel bus widths simultaneously, while the JTAG interface allows field reprogrammability when bus-protocol firmware needs revision. Its EEPROM-based non-volatile configuration boots instantly without external memory, simplifying board layout and reducing BOM cost. The 5 V tolerant I/Os interface cleanly with legacy 5 V peripherals.
Recomendado
Address Decoding and Chip Select Generation
For microprocessor systems with large memory maps, the EPM9560RI240-20C's 560 macrocells and 191 I/Os handle complex address decoding and chip-select generation across wide address buses. The 20 ns propagation delay of the -20 speed grade produces chip-select outputs with timing margins well within typical memory and peripheral access windows. Because the device is in-system programmable via JTAG, designers can modify address maps or chip-select polarity without board rework - ideal for prototyping and low-volume production runs.
Recomendado
High-Speed State Machine Controllers
The EPM9560RI240-20C implements complex Moore or Mealy state machines in deterministic, parallel hardware that runs up to 100 MHz internally. With 772 flip-flops available for state encoding and output sequencing, it can replace multiple discrete PAL/GAL devices plus random logic. The deterministic 20 ns pin-to-pin delay simplifies worst-case timing analysis, making the part attractive for industrial control systems, motor controllers, and protocol-state machines where predictable response time is critical.
Recomendado
Industrial Control and Instrumentation
In industrial control cabinets, the EPM9560RI240-20C delivers reliable glue logic and protocol conversion with the instant-on behavior required for deterministic system startup. Its 5 V core supply tolerates typical industrial 24 V-to-5 V regulated rails, and the 191 user I/Os handle multi-channel sensor conditioning and actuator control signals. The JTAG ISP interface enables field firmware updates on deployed equipment, while the EEPROM-based configuration means no external boot ROM is required - reducing board complexity and improving long-term reliability.
Recomendado
Legacy System Modernization
The EPM9560RI240-20C is widely used to modernize legacy 5 V systems by consolidating dozens of discrete 74F/74LS/74HC logic devices into a single programmable part. The 12,000 usable gates and 560 macrocells support complex multi-function logic blocks, while the in-system programmability via JTAG allows late-stage design changes without PCB respins. Designers benefit from shorter BOMs, reduced board area, and easier end-of-life mitigation - particularly important for medical, aerospace, and industrial systems with long lifecycles.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM9560RI240-20C — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM9560RI240-20 | EPM9560RI240-15C | EPM9560RI240-10 | EPM9480RC240-20 | EPM9480RC240-20C |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Macrocells | 560 | 560 | 560 | 560 | 480 | 480 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 10,000 | 10,000 |
| Propagation Delay (tPD) | 20 ns (-20 grade) | 20 ns (-20) | 15 ns (-15 grade) | 10 ns (-10 grade) | 20 ns (-20) | 20 ns (-20) |
| User I/Os | 191 | 191 | 191 | 191 | 191 | 191 |
| Operating Temperature | 0 to +70 °C (commercial) | Industrial / wider | 0 to +70 °C (commercial) | Industrial / wider | Industrial / wider | 0 to +70 °C (commercial) |
Principais diferenciais
- Highest density in the MAX 9000 family (vs EPM9480RC240-20C)
- Commercial temperature grade at lower cost (vs EPM9560RI240-20)
- Standard -20 speed grade balances cost and timing margin (vs EPM9560RI240-10)
Notas de projeto
The EPM9560RI240-20C requires a stable 5 V VCCINT supply with adequate decoupling. Place one 0.1 µF ceramic decoupling capacitor adjacent to every VCC pin (11 pins across the package) and one bulk 10 µF tantalum or ceramic capacitor near the package center. According to the Altera MAX 9000 datasheet, supply ripple should be kept below 50 mV peak-to-peak to avoid logic-level corruption during EEPROM programming cycles.
Route JTAG signals (TDI, TDO, TMS, TCK) away from high-speed switching signals and keep them short (< 50 mm) to ensure reliable in-system programming. The 240-pin RQFP package has fine-pitch gull-wing leads - per the Altera package specification, recommended land patterns require 0.5 mm lead pitch with 0.3 mm stencil apertures for reflow. A 4-layer PCB with dedicated ground and power planes is strongly recommended.
Do not exceed the 5 V VCCINT maximum - the EPM9560RI240-20C is NOT a 3.3 V core device, only its I/O banks can be 3.3 V. Ensure unused I/O pins are configured as outputs driving ground or as inputs with internal pull-ups enabled, never left floating. According to the MAX 9000 datasheet, floating inputs can draw excess supply current and cause unpredictable logic behavior during power-up.
Informações de conformidade
EPM9560RI240-20C is a legacy Altera (now Intel) MAX 9000 CPLD in NRD status. Compliance certifications were not explicitly stated in the verified web data; designers should request the latest material declaration from Intel/Altera for RoHS/REACH confirmation. Not qualified to AEC-Q100 (commercial temperature grade only).
