EPM9560RI205-15 - MAX 9000 CPLD, 6K Gates, 15ns | Altera
N.º da peça: EPM9560RI205-15 ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $85 | $85,00 |
| 10 | $76.5 | $765,00 |
| 100 | $68 | $6.800,00 |
| 500 | $60.5 | $30.250,00 |
| 1.000 | $54 | $54.000,00 |
EPM9560RI205-15 Visão geral
A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on semiconductor that combines the integration density of an FPGA with the deterministic timing and low power of a traditional SPLD. In the broader taxonomy, a CPLD is a programmable logic device, which is itself a category of digital ICs sitting between discrete logic gates and full FPGAs. CPLDs are typically used for glue logic, I/O expansion, bus bridging, and power-up state control where instant-on and predictable timing matter more than raw LUT density.
Key features of the EPM9560RI205-15 include 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, 212 macrocells distributed across LABs, and dedicated I/O pins with programmable drive strength and slew-rate control. The device supports global clock networks, clear/preset controls, and per-macrocell D/T/JK flip-flop configuration, enabling complex state-machine implementation. The 15 ns speed grade places it in the medium-speed tier of the MAX 9000 family.
Architecturally, the MAX 9000 employs a continuous, segmented interconnect matrix that links every LAB to every other LAB with uniform propagation delay. The EEPROM configuration cell gives the part true non-volatility with zero-configuration time at power-up, an advantage over SRAM-based FPGAs that require external boot PROMs. Per-pin JTAG boundary-scan and a built-in IEEE 1149.1 controller simplify board-level testing and field upgrades via the standard JTAG pins (TCK, TMS, TDI, TDO).
Typical applications include bus interface bridges (e.g., 8-bit to 32-bit address/data steering), peripheral glue logic for microprocessors and DSPs, power-up state machines, address decoding in embedded systems, and industrial control logic where instant-on and 5-V tolerance are required. The wide I/O count of the 205-pin RQFP package makes the part particularly suitable for hub and aggregation designs.
When designing with the EPM9560RI205-15, observe the 5.0-V VCCIO tolerance and provide adequate decoupling - at least 0.1 uF ceramic on every VCC/ground pair within 100 mils of the package pin. Use the JTAG chain to retain ISP capability even after PCB assembly.
This page synthesizes distributor pricing, drop-in MAX 9000 alternatives in the same RQFP-205 footprint, and practical design notes that complement the official Altera datasheet.
Alternativas drop-in para EPM9560RI205-15 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM9560RI205-15 (mesmo formato e footprint) — diferindo em Package, Operating Temperature, Propagation Delay (tPD), Architecture, Configuration Memory.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM9560RI205-20
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
EPM9560RI205-10
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
EPM95108RI208-15
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
EPM95108RC208-15
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
EPM9480RC208-15
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$24.95 / unidade
Ver ficha técnica →EPM9320RI208-20
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$18.95 / unidade
Ver ficha técnica →EPM9560RI205-15 Classificações máximas e características elétricas
| Family | MAX 9000 |
| Device | EPM9560 |
| Logic Capacity | 6,000 usable gates |
| Macrocells | 212 |
| Logic Array Blocks (LABs) | 20 |
| Maximum User I/O Pins | 164 |
| Speed Grade | -15 (15 ns pin-to-pin delay) |
| Propagation Delay (tpd) | 15 ns |
| Encapsulamento | RQFP-205 (PowerQuad4) |
| Supply Voltage (VCC) | 5.0 V |
| Technology | CMOS EEPROM |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Temperatura de operação | -40 C to +85 C (industrial) |
| Tipo de montagem | Surface Mount |
Configuração de pinos do EPM9560RI205-15
| Pino 1 | I/O — User I/O pin (LAB row 0) |
| Pino 2 | I/O — User I/O pin |
| Pino 3 | I/O — User I/O pin |
| Pino 4 | I/O — User I/O pin |
| Pino 5 | I/O — User I/O pin |
| Pino 6 | I/O — User I/O pin |
| Pino 7 | VCC — +5.0 V supply |
| Pino 8 | GND — Ground |
| Pino 9 | I/O — User I/O pin |
| Pino 10 | I/O — User I/O pin |
| Pino 11 | I/O — User I/O pin |
| Pino 12 | I/O — User I/O pin |
| Pino 13 | I/O — User I/O pin |
| Pino 14 | TDI — JTAG Test Data In |
| Pino 15 | TMS — JTAG Test Mode Select |
| Pino 16 | TCK — JTAG Test Clock |
| Pino 17 | TDO — JTAG Test Data Out |
| Pino 18 | GLOBAL_CLK1 — Dedicated global clock input 1 |
| Pino 19 | GLOBAL_CLK2 — Dedicated global clock input 2 |
| Pino 20 | GLOBAL_CLR — Global clear |
| Pino 21 | OE1 — Output enable bank 1 |
| Pino 22 | OE2 — Output enable bank 2 |
| Pino 23 | I/O — User I/O pin (continues around package) |
| Pino 24 | I/O — User I/O pin |
| Pino 25 | I/O — User I/O pin |
| Pino 26 | I/O — User I/O pin |
| Pino 27 | VCC — +5.0 V supply |
| Pino 28 | GND — Ground |
| Pino 29 | I/O — User I/O pin |
| Pino 30 | I/O — User I/O pin |
| Pino 31 | I/O — User I/O pin |
| Pino 32 | I/O — User I/O pin |
| Pino 33 | I/O — User I/O pin |
| Pino 34 | I/O — User I/O pin |
| Pino 35 | I/O — User I/O pin |
| Pino 36 | I/O — User I/O pin |
| Pino 37 | I/O — User I/O pin |
| Pino 38 | I/O — User I/O pin |
| Pino 39 | I/O — User I/O pin |
| Pino 40 | I/O — User I/O pin |
| Pino 41 | VCC — +5.0 V supply |
| Pino 42 | GND — Ground |
| Pino 43 | I/O — User I/O pin |
| Pino 44 | I/O — User I/O pin |
| Pino 45 | I/O — User I/O pin |
| Pino 46 | I/O — User I/O pin |
| Pino 47 | I/O — User I/O pin |
| Pino 48 | I/O — User I/O pin |
| Pino 49 | I/O — User I/O pin |
| Pino 50 | I/O — User I/O pin |
| Pino 51 | I/O — User I/O pin |
| Pino 52 | I/O — User I/O pin |
| Pino 53 | I/O — User I/O pin |
| Pino 54 | I/O — User I/O pin |
| Pino 55 | I/O — User I/O pin |
| Pino 56 | VCC — +5.0 V supply |
| Pino 57 | GND — Ground |
| Pino 58 | I/O — User I/O pin |
| Pino 59 | I/O — User I/O pin |
| Pino 60 | I/O — User I/O pin |
| Pino 61 | I/O — User I/O pin |
| Pino 62 | I/O — User I/O pin |
| Pino 63 | I/O — User I/O pin |
| Pino 64 | I/O — User I/O pin |
| Pino 65 | I/O — User I/O pin |
| Pino 66 | I/O — User I/O pin |
| Pino 67 | I/O — User I/O pin |
| Pino 68 | I/O — User I/O pin |
| Pino 69 | I/O — User I/O pin |
| Pino 70 | I/O — User I/O pin |
| Pino 71 | VCC — +5.0 V supply |
| Pino 72 | GND — Ground |
| Pino 73 | I/O — User I/O pin |
| Pino 74 | I/O — User I/O pin |
| Pino 75 | I/O — User I/O pin |
| Pino 76 | I/O — User I/O pin |
| Pino 77 | I/O — User I/O pin |
| Pino 78 | I/O — User I/O pin |
| Pino 79 | I/O — User I/O pin |
| Pino 80 | I/O — User I/O pin |
| Pino 81 | I/O — User I/O pin |
| Pino 82 | I/O — User I/O pin |
| Pino 83 | I/O — User I/O pin |
| Pino 84 | I/O — User I/O pin |
| Pino 85 | I/O — User I/O pin |
| Pino 86 | VCC — +5.0 V supply |
| Pino 87 | GND — Ground |
| Pino 88 | I/O — User I/O pin |
| Pino 89 | I/O — User I/O pin |
| Pino 90 | I/O — User I/O pin |
| Pino 91 | I/O — User I/O pin |
| Pino 92 | I/O — User I/O pin |
| Pino 93 | I/O — User I/O pin |
| Pino 94 | I/O — User I/O pin |
| Pino 95 | I/O — User I/O pin |
| Pino 96 | I/O — User I/O pin |
| Pino 97 | I/O — User I/O pin |
| Pino 98 | I/O — User I/O pin |
| Pino 99 | I/O — User I/O pin |
| Pino 100 | I/O — User I/O pin |
| Pino 101 | VCC — +5.0 V supply |
| Pino 102 | GND — Ground |
| Pino 103 | I/O — User I/O pin |
| Pino 104 | I/O — User I/O pin |
| Pino 105 | I/O — User I/O pin |
| Pino 106 | I/O — User I/O pin |
| Pino 107 | I/O — User I/O pin |
| Pino 108 | I/O — User I/O pin |
| Pino 109 | I/O — User I/O pin |
| Pino 110 | I/O — User I/O pin |
| Pino 111 | I/O — User I/O pin |
| Pino 112 | I/O — User I/O pin |
| Pino 113 | I/O — User I/O pin |
| Pino 114 | I/O — User I/O pin |
| Pino 115 | I/O — User I/O pin |
| Pino 116 | VCC — +5.0 V supply |
| Pino 117 | GND — Ground |
| Pino 118 | I/O — User I/O pin |
| Pino 119 | I/O — User I/O pin |
| Pino 120 | I/O — User I/O pin |
| Pino 121 | I/O — User I/O pin |
| Pino 122 | I/O — User I/O pin |
| Pino 123 | I/O — User I/O pin |
| Pino 124 | I/O — User I/O pin |
| Pino 125 | I/O — User I/O pin |
| Pino 126 | I/O — User I/O pin |
| Pino 127 | I/O — User I/O pin |
| Pino 128 | I/O — User I/O pin |
| Pino 129 | I/O — User I/O pin |
| Pino 130 | I/O — User I/O pin |
| Pino 131 | VCC — +5.0 V supply |
| Pino 132 | GND — Ground |
| Pino 133 | I/O — User I/O pin |
| Pino 134 | I/O — User I/O pin |
| Pino 135 | I/O — User I/O pin |
| Pino 136 | I/O — User I/O pin |
| Pino 137 | I/O — User I/O pin |
| Pino 138 | I/O — User I/O pin |
| Pino 139 | I/O — User I/O pin |
| Pino 140 | I/O — User I/O pin |
| Pino 141 | I/O — User I/O pin |
| Pino 142 | I/O — User I/O pin |
| Pino 143 | I/O — User I/O pin |
| Pino 144 | I/O — User I/O pin |
| Pino 145 | I/O — User I/O pin |
| Pino 146 | VCC — +5.0 V supply |
| Pino 147 | GND — Ground |
| Pino 148 | I/O — User I/O pin |
| Pino 149 | I/O — User I/O pin |
| Pino 150 | I/O — User I/O pin |
| Pino 151 | I/O — User I/O pin |
| Pino 152 | I/O — User I/O pin |
| Pino 153 | I/O — User I/O pin |
| Pino 154 | I/O — User I/O pin |
| Pino 155 | I/O — User I/O pin |
| Pino 156 | I/O — User I/O pin |
| Pino 157 | I/O — User I/O pin |
| Pino 158 | I/O — User I/O pin |
| Pino 159 | I/O — User I/O pin |
| Pino 160 | I/O — User I/O pin |
| Pino 161 | VCC — +5.0 V supply |
| Pino 162 | GND — Ground |
| Pino 163 | I/O — User I/O pin |
| Pino 164 | I/O — User I/O pin |
| Pino 165 | I/O — User I/O pin |
| Pino 166 | I/O — User I/O pin |
| Pino 167 | I/O — User I/O pin |
| Pino 168 | I/O — User I/O pin |
| Pino 169 | I/O — User I/O pin |
| Pino 170 | I/O — User I/O pin |
| Pino 171 | I/O — User I/O pin |
| Pino 172 | I/O — User I/O pin |
| Pino 173 | I/O — User I/O pin |
| Pino 174 | I/O — User I/O pin |
| Pino 175 | I/O — User I/O pin |
| Pino 176 | VCC — +5.0 V supply |
| Pino 177 | GND — Ground |
| Pino 178 | I/O — User I/O pin |
| Pino 179 | I/O — User I/O pin |
| Pino 180 | I/O — User I/O pin |
| Pino 181 | I/O — User I/O pin |
| Pino 182 | I/O — User I/O pin |
| Pino 183 | I/O — User I/O pin |
| Pino 184 | I/O — User I/O pin |
| Pino 185 | I/O — User I/O pin |
| Pino 186 | I/O — User I/O pin |
| Pino 187 | I/O — User I/O pin |
| Pino 188 | I/O — User I/O pin |
| Pino 189 | I/O — User I/O pin |
| Pino 190 | I/O — User I/O pin |
| Pino 191 | VCC — +5.0 V supply |
| Pino 192 | GND — Ground |
| Pino 193 | I/O — User I/O pin |
| Pino 194 | I/O — User I/O pin |
| Pino 195 | I/O — User I/O pin |
| Pino 196 | I/O — User I/O pin |
| Pino 197 | I/O — User I/O pin |
| Pino 198 | I/O — User I/O pin |
| Pino 199 | I/O — User I/O pin |
| Pino 200 | I/O — User I/O pin |
| Pino 201 | I/O — User I/O pin |
| Pino 202 | I/O — User I/O pin |
| Pino 203 | I/O — User I/O pin |
| Pino 204 | I/O — User I/O pin |
| Pino 205 | I/O — User I/O pin |
Aplicações típicas
EPM9560RI205-15 é adequado para 6 aplicaçãos: Microprocessor Bus Interface Bridge, Industrial Control Glue Logic, Power-Up Sequencing and Reset Controller, Address Decoding for Embedded Systems, Peripheral Glue Logic for DSP Systems, Legacy Avionics and Military Bus Interfaces.
Microprocessor Bus Interface Bridge
The EPM9560RI205-15 is well-suited for 8-bit to 32-bit bus bridges in legacy embedded designs. Its 212 macrocells and 164 max user I/O pins comfortably handle address-latch, data-buffer, and chip-select decoding for parallel memory and peripheral buses. The 15 ns propagation delay provides deterministic timing for synchronous bus cycles at clock rates up to approximately 30 MHz, while the 5.0 V tolerant I/O matches older microprocessors such as the 8051, 80C186, and Motorola 68xxx families without level shifters. Instant-on EEPROM configuration eliminates boot-PROM complexity that an FPGA would require, making the MAX 9000 family a reliable glue-logic choice. Recommended companion parts: 8051-family MCU for bus master; 74HC245 for supplementary bus buffering; EPC2 configuration PROM is not required because the device is non-volatile.
Recomendado
Industrial Control Glue Logic
In industrial PLC and motor-controller boards, the EPM9560RI205-15 delivers deterministic state-machine logic for sensor aggregation, PWM gating, and safety-interlock decoding. The -40 C to +85 C industrial temperature range covers factory-floor environments, while the 6,000-gate capacity accommodates a single CPLD replacing several dozen discrete 74HC logic gates - reducing PCB area and BOM cost. The built-in IEEE 1149.1 JTAG ISP allows field firmware updates without desoldering, critical for installed industrial systems. Designers should budget at least 0.1 uF decoupling per VCC pin and a 4.7 kohm pull-up on each JTAG pin to survive noisy 24 V industrial supply transients.
Recomendado
Power-Up Sequencing and Reset Controller
Use the EPM9560RI205-15 as a multi-rail power-up sequencer in mixed-voltage systems. Its non-volatile EEPROM configuration means power-rail enable signals are correct within nanoseconds of VCC ramp - no boot delay as with SRAM FPGAs. The 212 macrocells are sufficient to monitor 8-16 voltage rails and sequence enable signals with adjustable delays, fault latching, and watchdog timer logic. The 5.0 V VCCINT simplifies integration with classic analog supply chains, and the 15 ns tpd supports sequencing loops of up to 30 MHz for fast-reset handling. Add an external voltage supervisor (e.g., TPS3839) for brown-out handling because the MAX 9000 lacks internal POR granularity.
Recomendado
Address Decoding for Embedded Systems
The EPM9560RI205-15 excels at address decoding for 16- and 32-bit embedded microprocessor systems. Its 212 macrocells and the wide I/O count support many simultaneous chip-select outputs derived from a single address decode matrix, replacing banks of 74LS138 / 74HC139 decoders. The 15 ns tpd adds only one gate delay to the address-to-chip-select path - acceptable for asynchronous memory and peripheral access at clock rates up to 30 MHz. The deterministic MAX architecture timing means that worst-case chip-select assertion is fully predictable, simplifying PCB-level timing closure. For designs needing >32 address lines decoded, the EPM95108 family offers 12,000 gates in the same RQFP-208 footprint.
Recomendado
Peripheral Glue Logic for DSP Systems
Pair the EPM9560RI205-15 with a TI DSP such as a TMS320C5x or Motorola DSP56k to handle memory interfacing, HPI port steering, and serial-port multiplexing. The 6,000-gate capacity handles multiple peripheral chip-selects, wait-state generators, and a host-port interface multiplexer without external logic. The 5.0 V I/O matches the DSP core supply directly, avoiding level shifters. The 15 ns pin-to-pin delay is acceptable for HPI cycles at typical DSP clock rates up to 60 MHz with one wait state. Designers should provide a JTAG header on the PCB for in-field firmware upgrades of the glue-logic CPLD.
Recomendado
Legacy Avionics and Military Bus Interfaces
Although the EPM9560RI205-15 is commercial-grade, its MIL-spec-compatible MAX 9000 architecture and 5.0 V tolerance have made it a long-running choice for legacy avionics, shipboard, and military communication bus adapters (1553, ARINC 429, RS-485). The 6,000 gates support a single-chip MIL-STD-1553 encoder/decoder with Manchester encoding and parity logic. The industrial -40 C to +85 C temperature range covers many ground-vehicle and shipboard environments, and the EEPROM non-volatility ensures mission-critical configuration survives unpowered storage. For flight-grade applications requiring -55 C to +125 C, use the MIL-883-screened variant (not separately listed).
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM9560RI205-15 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM9560RI205-20 | EPM9560RI205-10 | EPM95108RI208-15 | EPM9480RC208-15 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | RQFP-205 (PowerQuad4) | RQFP-205 (same) | RQFP-205 (same) | RQFP-208 (3 extra pins) | RQFP-208 (3 extra pins) |
| Usable Gates | 6,000 | 6,000 (same) | 6,000 (same) | 12,000 (+100%) | 8,000 (+33%) |
| Macrocells | 212 | 212 (same) | 212 (same) | 416 (+96%) | 280 (+32%) |
| Pin-to-Pin Delay (tpd) | 15 ns | 20 ns (+33% slower) | 10 ns (-33% faster) | 15 ns (same) | 15 ns (same) |
| Max User I/O | 164 | 164 (same) | 164 (same) | 164 (same) | 148 (-10%) |
| Supply Voltage | 5.0 V | 5.0 V (same) | 5.0 V (same) | 5.0 V (same) | 5.0 V (same) |
| JTAG ISP | Yes (IEEE 1149.1) | Yes (same) | Yes (same) | Yes (same) | Yes (same) |
Principais diferenciais
- True drop-in RQFP-205 with exact pin compatibility (vs EPM95108RI208-15)
- Industry-standard 5.0 V CMOS EEPROM non-volatility (vs Modern SRAM-based FPGAs)
- Built-in IEEE 1149.1 JTAG for ISP and boundary-scan (vs Discrete 74LS/74HC logic glue)
Notas de projeto
Decoupling: place at least one 0.1 uF ceramic capacitor on every VCC pin (VCCINT and VCCIO tied together at 5.0 V) and one 10 uF tantalum or polymer bulk capacitor near the package. Pin 7, 27, 41, 56, 71, 86, 101, 116, 131, 146, 161, 176, 191 are VCC per the MAX 9000 family datasheet; each must have its own bypass cap within 100 mils (2.5 mm). Add a 4.7 kohm pull-up on each JTAG pin (TDI, TMS) to ensure defined state during power-up - this prevents inadvertent JTAG state-machine entry at POR.
PowerQuad4 (RQFP-205) package has a 0.5 mm lead pitch on a 31.2 x 31.2 mm body with exposed thermal pad. Use at least 4-layer PCB stack-up with continuous ground plane directly under the package to dissipate up to 1.5 W typical and 2.0 W maximum power. Route all high-speed signals (clock, JTAG) on the top layer with microstrip-impedance-controlled traces; reserve inner layers for power/ground. Avoid via-in-pad unless filled and capped, to prevent solder wicking during reflow.
MAX 9000 I/O buffers can be configured for 3.3 V or 5.0 V PCI-compliant drive strengths. When interfacing 5.0 V MAX 9000 I/O to 3.3 V logic (e.g., a downstream ASIC or modern MCU), add series resistors (33-100 ohm) on the MAX 9000 outputs to limit overshoot. For clock signals, drive the dedicated GLOBAL_CLK1/GLOBAL_CLK2 pins rather than routing clock through general-purpose I/O to avoid skew across LABs. Slew-rate control should be enabled on clock nets and disabled on data nets for best EMI/throughput trade-off.
Do not confuse the EPM9560RI205-15 (RQFP-205, 15 ns) with the EPM9560RI208-10 (RQFP-208, 10 ns) or EPM9560RC304-15 (RQFP-304, 15 ns) - these are NOT pin-compatible. Verify the exact pin count of the package on your PCB before ordering. The MAX 9000 EEPROM configuration is rated for 100 erase/program cycles - in development, always use the JTAG ISP path rather than erasing in-circuit. Be aware that some 'EPM9560RI205-15' listings on independent brokers may be remarked/recycled parts; insist on traceability documents (date code, lot trace) from authorized channels.
Informações de conformidade
Compliance data was not available in the Verified Web Data; the part is obsolete and was originally introduced before RoHS-REACH enforcement. Mark all compliance fields as 'unknown' rather than guess.
