AD9500BP vs AD9500WAFER Comparação
Comparação detalhada lado a lado de AD9500BP por Analog Devices e AD9500WAFER por Analog Devices. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | AD9500BP | AD9500WAFER |
|---|---|---|
| Marca | Analog Devices | Analog Devices |
| Categoria | Clock & Timing | Clock & Timing |
| Status do ciclo de vida | Unknown | Ativo |
| Product Type | Digitally programmable delay generator | — |
| Delay Resolution | 10 ps | — |
| Full-Scale Delay Range | 10 ns | — |
| Programming Interface | 8-bit digital code | — |
| Input Type | Fully differential inputs | — |
| Input Logic Support | Single-ended or differential ECL circuits | — |
| Tipo de saída | Complementary ECL output | — |
| Output Feature | Q/R parallel output circuit | — |
| Trigger Inputs | Separate trigger input | — |
| Reset Inputs | Separate reset input | — |
| Power Consumption | Low power, mW class | — |
| Military Availability | Versions compliant with MIL-STD-883 available | — |
| Encapsulamento | 28-LCC J-lead surface-mount package | — |
| Package Family | Lead-chip carrier ceramic surface-mount package | — |
| Ceramic DIP Variant | 24-pin ceramic skinny DIP, 0.3 inch package width | — |
| Temperatura de operação | [DATA_NEEDED: operating temperature range] | — |
| Tensão de alimentação | [DATA_NEEDED: supply voltage] | +5 V single supply |
| Propagation Delay | [DATA_NEEDED: propagation delay] | — |
| Jitter | [DATA_NEEDED: jitter] | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of bare die] |
| Manufacturer | — | Analog Devices |
| Part Number | — | AD9500WAFER |
| Part Type | — | Digitally Programmable Delay Generator |
| Package / Form Factor | — | IC Die (bare silicon wafer form) |
| Programming Resolution | — | 8 bits digital delay programming |
| Analog Fine Adjust | — | Yes (external analog sweep / vernier input) |
| Trigger Input Level | — | CMOS / TTL compatible |
| Output Level | — | CMOS / TTL compatible |
| Supply Voltage Tolerance | — | [DATA_NEEDED: supply voltage tolerance] |
| Faixa de temperatura de operação | — | [DATA_NEEDED: operating temperature range] |
| Maximum Delay Range | — | [DATA_NEEDED: maximum delay range in nanoseconds/microseconds] |
| Minimum Delay Step | — | [DATA_NEEDED: minimum delay step in picoseconds] |
| Trigger-to-Output Jitter | — | [DATA_NEEDED: trigger-to-output jitter] |
| ESD Rating (Human Body Model) | — | [DATA_NEEDED: HBM ESD rating - die handling only] |
| Package Reference (Packaged Sibling) | — | 24-pin ceramic Skinny DIP, 28-pin surface mount (per packaged AD9500 datasheet) |
| Packaged Sibling | — | AD9500 (ceramic DIP and SOIC packaged parts available) |
| Tipo de montagem | — | Die attach / wire bond / flip-chip (integrator-dependent) |
| Military / 883B Sibling | — | AD9500/883B available per MIL-STD-883 |