AD9500BP vs AD9500WAFER Vergleich
Detaillierter Direktvergleich von AD9500BP von Analog Devices und AD9500WAFER von Analog Devices. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | AD9500BP | AD9500WAFER |
|---|---|---|
| Marke | Analog Devices | Analog Devices |
| Kategorie | Clock & Timing | Clock & Timing |
| Lebenszyklusstatus | Unknown | Aktiv |
| Product Type | Digitally programmable delay generator | — |
| Delay Resolution | 10 ps | — |
| Full-Scale Delay Range | 10 ns | — |
| Programming Interface | 8-bit digital code | — |
| Input Type | Fully differential inputs | — |
| Input Logic Support | Single-ended or differential ECL circuits | — |
| Ausgangstyp | Complementary ECL output | — |
| Output Feature | Q/R parallel output circuit | — |
| Trigger Inputs | Separate trigger input | — |
| Reset Inputs | Separate reset input | — |
| Power Consumption | Low power, mW class | — |
| Military Availability | Versions compliant with MIL-STD-883 available | — |
| Gehäuse | 28-LCC J-lead surface-mount package | — |
| Package Family | Lead-chip carrier ceramic surface-mount package | — |
| Ceramic DIP Variant | 24-pin ceramic skinny DIP, 0.3 inch package width | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | — |
| Versorgungsspannung | [DATA_NEEDED: supply voltage] | +5 V single supply |
| Propagation Delay | [DATA_NEEDED: propagation delay] | — |
| Jitter | [DATA_NEEDED: jitter] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of bare die] |
| Manufacturer | — | Analog Devices |
| Part Number | — | AD9500WAFER |
| Part Type | — | Digitally Programmable Delay Generator |
| Package / Form Factor | — | IC Die (bare silicon wafer form) |
| Programming Resolution | — | 8 bits digital delay programming |
| Analog Fine Adjust | — | Yes (external analog sweep / vernier input) |
| Trigger Input Level | — | CMOS / TTL compatible |
| Output Level | — | CMOS / TTL compatible |
| Supply Voltage Tolerance | — | [DATA_NEEDED: supply voltage tolerance] |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |
| Maximum Delay Range | — | [DATA_NEEDED: maximum delay range in nanoseconds/microseconds] |
| Minimum Delay Step | — | [DATA_NEEDED: minimum delay step in picoseconds] |
| Trigger-to-Output Jitter | — | [DATA_NEEDED: trigger-to-output jitter] |
| ESD Rating (Human Body Model) | — | [DATA_NEEDED: HBM ESD rating - die handling only] |
| Package Reference (Packaged Sibling) | — | 24-pin ceramic Skinny DIP, 28-pin surface mount (per packaged AD9500 datasheet) |
| Packaged Sibling | — | AD9500 (ceramic DIP and SOIC packaged parts available) |
| Montageart | — | Die attach / wire bond / flip-chip (integrator-dependent) |
| Military / 883B Sibling | — | AD9500/883B available per MIL-STD-883 |