AD9500BP vs AD9500WAFER 비교
다음의 상세 나란히 비교: AD9500BP 제조: Analog Devices 및 AD9500WAFER 제조: Analog Devices. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | AD9500BP | AD9500WAFER |
|---|---|---|
| 브랜드 | Analog Devices | Analog Devices |
| 카테고리 | Clock & Timing | Clock & Timing |
| 수명 주기 상태 | Unknown | 활성 |
| Product Type | Digitally programmable delay generator | — |
| Delay Resolution | 10 ps | — |
| Full-Scale Delay Range | 10 ns | — |
| Programming Interface | 8-bit digital code | — |
| Input Type | Fully differential inputs | — |
| Input Logic Support | Single-ended or differential ECL circuits | — |
| 출력 유형 | Complementary ECL output | — |
| Output Feature | Q/R parallel output circuit | — |
| Trigger Inputs | Separate trigger input | — |
| Reset Inputs | Separate reset input | — |
| Power Consumption | Low power, mW class | — |
| Military Availability | Versions compliant with MIL-STD-883 available | — |
| 패키지 | 28-LCC J-lead surface-mount package | — |
| Package Family | Lead-chip carrier ceramic surface-mount package | — |
| Ceramic DIP Variant | 24-pin ceramic skinny DIP, 0.3 inch package width | — |
| 동작 온도 | [DATA_NEEDED: operating temperature range] | — |
| 공급 전압 | [DATA_NEEDED: supply voltage] | +5 V single supply |
| Propagation Delay | [DATA_NEEDED: propagation delay] | — |
| Jitter | [DATA_NEEDED: jitter] | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of bare die] |
| Manufacturer | — | Analog Devices |
| Part Number | — | AD9500WAFER |
| Part Type | — | Digitally Programmable Delay Generator |
| Package / Form Factor | — | IC Die (bare silicon wafer form) |
| Programming Resolution | — | 8 bits digital delay programming |
| Analog Fine Adjust | — | Yes (external analog sweep / vernier input) |
| Trigger Input Level | — | CMOS / TTL compatible |
| Output Level | — | CMOS / TTL compatible |
| Supply Voltage Tolerance | — | [DATA_NEEDED: supply voltage tolerance] |
| 동작 온도 범위 | — | [DATA_NEEDED: operating temperature range] |
| Maximum Delay Range | — | [DATA_NEEDED: maximum delay range in nanoseconds/microseconds] |
| Minimum Delay Step | — | [DATA_NEEDED: minimum delay step in picoseconds] |
| Trigger-to-Output Jitter | — | [DATA_NEEDED: trigger-to-output jitter] |
| ESD Rating (Human Body Model) | — | [DATA_NEEDED: HBM ESD rating - die handling only] |
| Package Reference (Packaged Sibling) | — | 24-pin ceramic Skinny DIP, 28-pin surface mount (per packaged AD9500 datasheet) |
| Packaged Sibling | — | AD9500 (ceramic DIP and SOIC packaged parts available) |
| 실장 유형 | — | Die attach / wire bond / flip-chip (integrator-dependent) |
| Military / 883B Sibling | — | AD9500/883B available per MIL-STD-883 |