EP2A25F672I6 vs EP2A25F672I-7 Comparação
Comparação detalhada lado a lado de EP2A25F672I6 por Intel e EP2A25F672I-7 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP2A25F672I6 | EP2A25F672I-7 |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $178,00 | $171,00 |
| Family | APEX II | APEX II |
| Logic Elements (typical gates) | 25,000 | — |
| Fabric Architecture | SRAM-based LUT | — |
| Process Technology | 0.18 µm CMOS | 0.15 um |
| Encapsulamento | 672-ball FineLine BGA (FBGA-672) | 672-pin FC-FBGA |
| Core Voltage | 1.5 V | 1.5 V |
| Configuration Method | External SRAM configuration device (EPC series) | JTAG, Passive Serial, Active Serial |
| Temperature Grade | Industrial (-40 °C to +100 °C ambient) | Industrial (I) |
| Speed Grade | 6 | -7 |
| Embedded Memory | Embedded System Blocks (ESB), dual-port RAM / CAM | ESBs (Embedded System Blocks) |
| DSP Blocks | MultiCore dedicated multipliers | — |
| Boundary Scan | JTAG (IEEE 1149.1) compliant | — |
| Clock Management | Dedicated PLL / clock tree circuitry | — |
| I/O Bank Count | [DATA_NEEDED: number of user I/O banks] | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Nível MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Tipo de montagem | Surface Mount (BGA) | Surface Mount (Flip-Chip BGA) |
| Manufacturer | — | Intel (formerly Altera) |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| System Gates | — | 900K (approximately) |
| Logic Cells / Elements | — | 24,320 |
| Maximum Operating Frequency | — | 500 MHz |
| Temperatura de operação | — | -40C to +85C (Industrial) |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |