EP610DC-30 vs EP610IDC-10 Comparação

Comparação detalhada lado a lado de EP610DC-30 por Altera e EP610IDC-10 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EP610DC-30 EP610IDC-10
Marca Altera Intel
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida NRND Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $10,40 $8,85
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family EP610 (Classic Device Family) —
Macrocells 16 —
Logic Expanders 4 (4 product terms per macrocell) —
Usable Gates 300 —
Maximum Pipelined Clock Frequency 100 MHz —
Propagation Delay (tPD) 30 ns —
Dedicated Inputs 16 4
I/O Pins 16 (with output enable) 20
Encapsulamento 24-pin CERDIP (windowed) —
Tipo de montagem Through-Hole Through-hole
Speed Grade -30 (30 ns tPD) —
Technology CMOS EPROM CMOS, UV-erasable (windowed ceramic)
Programmability UV-erasable, windowed EPROM —
Security Bit Yes (protects design after programming) —
Output Modes Registered and Combinatorial —
Temperatura de operação Commercial (0C to +70C) —
Device Family — Altera Classic EPLD
Logic Capacity — 300 usable gates
Macrocell Count — 16 macrocells
Pin-to-Pin Logic Delay (tpd) — 10 ns
Maximum Counter Frequency (fCNT) — 100 MHz
Supply Voltage (VCC) — 5 V (nominal)
I/O Logic Compatibility — 100% TTL emulation
Package Type — 24-pin Ceramic DIP (CDIP)
Faixa de temperatura de operação — 0 °C to +70 °C (commercial)
Programmable Interconnect — Yes (on-chip)
In-System Programmability — Yes (via MAX+PLUS II)
Boundary-Scan Test — Yes (per device documentation)
Status RoHS — [DATA_NEEDED: RoHS status of CDIP-10 variant]

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