EP610DC-30 vs EP610IDC-10 Comparison
Detailed side-by-side comparison of EP610DC-30 by Altera and EP610IDC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-30 | EP610IDC-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $8.85 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | β |
| Family | EP610 (Classic Device Family) | β |
| Macrocells | 16 | β |
| Logic Expanders | 4 (4 product terms per macrocell) | β |
| Usable Gates | 300 | β |
| Maximum Pipelined Clock Frequency | 100 MHz | β |
| Propagation Delay (tPD) | 30 ns | β |
| Dedicated Inputs | 16 | 4 |
| I/O Pins | 16 (with output enable) | 20 |
| Package | 24-pin CERDIP (windowed) | β |
| Mounting Type | Through-Hole | Through-hole |
| Speed Grade | -30 (30 ns tPD) | β |
| Technology | CMOS EPROM | CMOS, UV-erasable (windowed ceramic) |
| Programmability | UV-erasable, windowed EPROM | β |
| Security Bit | Yes (protects design after programming) | β |
| Output Modes | Registered and Combinatorial | β |
| Operating Temperature | Commercial (0C to +70C) | β |
| Device Family | β | Altera Classic EPLD |
| Logic Capacity | β | 300 usable gates |
| Macrocell Count | β | 16 macrocells |
| Pin-to-Pin Logic Delay (tpd) | β | 10 ns |
| Maximum Counter Frequency (fCNT) | β | 100 MHz |
| Supply Voltage (VCC) | β | 5 V (nominal) |
| I/O Logic Compatibility | β | 100% TTL emulation |
| Package Type | β | 24-pin Ceramic DIP (CDIP) |
| Operating Temperature Range | β | 0 Β°C to +70 Β°C (commercial) |
| Programmable Interconnect | β | Yes (on-chip) |
| In-System Programmability | β | Yes (via MAX+PLUS II) |
| Boundary-Scan Test | β | Yes (per device documentation) |
| RoHS Status | β | [DATA_NEEDED: RoHS status of CDIP-10 variant] |