EP610DC-35 vs EP610DC-10 Comparação
Comparação detalhada lado a lado de EP610DC-35 por Altera e EP610DC-10 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP610DC-35 | EP610DC-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $18,40 | $7,95 |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Process Technology | CMOS | — |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| Encapsulamento | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin CDIP (Ceramic DIP, windowed) |
| Tipo de montagem | Through-Hole (DIP) | Through-Hole |
| Temperatura de operação | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | 0C to +70C (commercial) |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | — |
| Status RoHS | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | [DATA_NEEDED: not stated in verified web data] |
| Device Family | — | Altera Classic EPLD |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Speed Grade | — | -10 |
| Technology | — | CMOS, EPROM-based (UV-erasable) |
| Tensão de alimentação | — | 5 V (single supply) |
| I/O Pins | — | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |