EP910DC-40 vs EP910DI-35 Comparação

Comparação detalhada lado a lado de EP910DC-40 por Altera e EP910DI-35 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EP910DC-40 EP910DI-35
Marca Altera Altera
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Obsolete Ativo
Status do estoque In Stock In Stock
Preço unitário (USD) $13,95 $35,20
Device Family Classic EPLD (EP910 series) —
Architecture PAL-type AND/OR, UV-erasable CMOS —
Macrocells 24 24
Dedicated Inputs 12 10
Bidirectional I/O Pins 24 20
Total Inputs to Logic Array 36 —
Product Terms 240 maximum —
Maximum Propagation Delay (tPD) 40 ns —
Maximum Operating Frequency (fMAX) 25 MHz —
Global Clocks 2 —
Tensão de alimentação 5 V (typical for Classic EPLD family) —
Operating Temperature (Commercial) 0 °C to 70 °C —
Encapsulamento DIP-40 (ceramic, through-hole) CDIP-40 (Ceramic DIP with UV window)
Tipo de montagem Through-Hole Through-Hole
Status RoHS [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified]
Programming Method UV-erase + EPROM programmer; on-board logic test circuitry EPROM programmer + JEDEC fuse map
Product Type — EPLD (Erasable Programmable Logic Device)
Family — Altera Classic EPLD
Usable Gates — 450
Propagation Delay (tPD) — 35 ns
Maximum Toggle Frequency (fCNT) — 28.6 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
Supply Current (ICC) — 40 mA typical
Total Pins — 40
Temperatura de operação — -40C to +85C (industrial)
Technology — CMOS, UV-erasable EPROM
Erasure Method — UV light through quartz window
Logic Family — PAL-type AND/OR array with D flip-flops
Manufacturer — Original Altera; long-term authorized by Rochester Electronics, LLC

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