EP910DC-35 - 35ns 900-Gate CMOS UV PLD DIP-40 | Intel / Altera
N.º da peça: EP910DC-35 ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $14.1 | $1.410,00 |
| 500 | $12.4 | $6.200,00 |
| 1.000 | $10.95 | $10.950,00 |
EP910DC-35 Visão geral
A Programmable Logic Device (PLD) is a digital integrated circuit whose internal AND/OR array and output macrocell logic can be configured by the user to implement arbitrary combinational and registered Boolean functions, replacing discrete SSI/MSI gate packages. PLDs sit beneath FPGAs in the programmable-logic hierarchy and are subdivided into PAL-type (one-time programmable or UV-erasable), GAL/EPLD (electrically erasable CMOS) and CPLD (complex PLD, multiple macrocell blocks with central interconnect) families. The EP910 sits at the high end of the Classic EPLD family, providing register-intensive glue-logic integration for bus interface, address decoding and state-machine consolidation.
Key features of the EP910DC-35 include 35ns pin-to-pin propagation delay (the slowest speed grade of the EP910DC series), 24 flip-flop-equipped macrocells, JEDEC-standard fuse-map programming, a UV-erasable quartz window on the ceramic package for development iteration, and TTL-compatible I/O. Architecturally the EP910 uses a sum-of-products AND-OR array feeding a flexible macrocell block that can be configured as D, T, JK or SR flip-flop, or as combinational output with selectable polarity. The device is specified at 5V ±5% with 5.25V absolute maximum.
Typical applications include TTL/CMOS logic consolidation on VMEbus and Multibus adapter cards, address decoding for 8086/68000/80386 microcomputer boards, peripheral controllers (DMA, interrupt, wait-state generation), industrial state machines, and replacement of legacy 24-pin PAL glue-logic clusters. The ceramic DIP-40 windowed package makes the part especially suitable for prototype and low-volume production where in-house UV erase and reprogram cycles are practical.
Design consideration: the ceramic DIP-40 quartz-windowed package requires a UV eraser for reprogramming (typically 20-30 minutes of 12,000 µW/cm² short-wave UV). Production users should migrate to the OTP plastic DIP variant (EP910PC-35) once logic is frozen, or to the pin-compatible but electrically erasable 5ns MAX-class CPLD family when higher density is required.
This page synthesizes distributor stock and pricing, drop-in EP910 speed-grade alternatives from the same Classic EPLD family, and practical design notes that are not assembled in any single manufacturer datasheet, helping engineers source or substitute this legacy part with confidence.
Alternativas drop-in para EP910DC-35 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EP910DC-35 (mesmo formato e footprint) — diferindo em Package, Family, Operating Temperature, Architecture, Programming Method.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EP910DC-30
✅ Drop-In✓ Em estoque
$15.6 / unidade
Ver ficha técnica →EP910DC-25
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EP910PC-35
✅ Drop-In✓ Em estoque
$8.7 / unidade
Ver ficha técnica →EP910LC-35
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$18.75 / unidade
Ver ficha técnica →EP910DC-40
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$13.95 / unidade
Ver ficha técnica →EP910JC-35
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$9.95 / unidade
Ver ficha técnica →EP910DC-35 Classificações máximas e características elétricas
| Device Type | UV-Erasable CMOS PLD (PAL-type) |
| Family | Classic EPLD EP910 |
| Architecture | PAL-type sum-of-products AND-OR array |
| Usable Gates | 900 gates |
| Macrocells | 24 |
| Product Terms | 240 |
| Dedicated Inputs | 12 |
| I/O Pins | 24 |
| Total Inputs | 36 |
| Propagation Delay (tpd) | 35 ns |
| Frequência máxima de clock | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) |
| Temperatura de operação | 0 °C to +70 °C (commercial) |
| Encapsulamento | 40-pin CDIP (Ceramic DIP) with quartz window |
| Lead Pitch | 2.540 mm |
| Termination Style | Through-Hole |
| Programming Method | JEDEC fuse map via device programmer; UV erase |
| Technology | CMOS, UV-erasable EPROM cell |
| Status RoHS | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Lifecycle | Obsolete / last-time-buy from authorized distributors |
Configuração de pinos do EP910DC-35
| Pino 1 | I/O0 — Bidirectional macrocell I/O 0 |
| Pino 2 | I/O1 — Bidirectional macrocell I/O 1 |
| Pino 3 | I/O2 — Bidirectional macrocell I/O 2 |
| Pino 4 | I/O3 — Bidirectional macrocell I/O 3 |
| Pino 5 | I/O4 — Bidirectional macrocell I/O 4 |
| Pino 6 | I/O5 — Bidirectional macrocell I/O 5 |
| Pino 7 | I/O6 — Bidirectional macrocell I/O 6 |
| Pino 8 | I/O7 — Bidirectional macrocell I/O 7 |
| Pino 9 | I/O8 — Bidirectional macrocell I/O 8 |
| Pino 10 | I/O9 — Bidirectional macrocell I/O 9 |
| Pino 11 | I/O10 — Bidirectional macrocell I/O 10 |
| Pino 12 | I/O11 — Bidirectional macrocell I/O 11 |
| Pino 13 | IN0 — Dedicated input 0 |
| Pino 14 | IN1 — Dedicated input 1 |
| Pino 15 | IN2 — Dedicated input 2 |
| Pino 16 | IN3 — Dedicated input 3 |
| Pino 17 | IN4 — Dedicated input 4 |
| Pino 18 | IN5 — Dedicated input 5 |
| Pino 19 | IN6 — Dedicated input 6 |
| Pino 20 | IN7 — Dedicated input 7 |
| Pino 21 | IN8 — Dedicated input 8 |
| Pino 22 | IN9 — Dedicated input 9 |
| Pino 23 | IN10 — Dedicated input 10 |
| Pino 24 | IN11 — Dedicated input 11 |
| Pino 25 | I/O12 — Bidirectional macrocell I/O 12 |
| Pino 26 | I/O13 — Bidirectional macrocell I/O 13 |
| Pino 27 | I/O14 — Bidirectional macrocell I/O 14 |
| Pino 28 | I/O15 — Bidirectional macrocell I/O 15 |
| Pino 29 | I/O16 — Bidirectional macrocell I/O 16 |
| Pino 30 | I/O17 — Bidirectional macrocell I/O 17 |
| Pino 31 | I/O18 — Bidirectional macrocell I/O 18 |
| Pino 32 | I/O19 — Bidirectional macrocell I/O 19 |
| Pino 33 | I/O20 — Bidirectional macrocell I/O 20 |
| Pino 34 | I/O21 — Bidirectional macrocell I/O 21 |
| Pino 35 | I/O22 — Bidirectional macrocell I/O 22 |
| Pino 36 | I/O23 — Bidirectional macrocell I/O 23 |
| Pino 37 | GND — Ground |
| Pino 38 | VCC — +5V power supply |
| Pino 39 | VCC — +5V power supply |
| Pino 40 | VCC — +5V power supply |
Aplicações típicas
EP910DC-35 é adequado para 6 aplicaçãos: VMEbus Adapter Card Address Decoding, Multibus I Glue-Logic Consolidation, 8086/80286/80386 Peripheral Controller PLD, Industrial State-Machine Controller, Vintage PAL Cluster Replacement, Prototype and Development Platform.
VMEbus Adapter Card Address Decoding
The EP910DC-35 fits VMEbus address-decoding applications because it provides 24 macrocells and 240 product terms - sufficient capacity to fully decode the 16-bit VMEbus address plus address-modifier lines, DTACK generation and interrupt acknowledge logic in a single device. Its 35 ns tpd is well within VMEbus timing budgets (typical access time 40-70 ns), and the CDIP-40 ceramic package with through-hole leads is the canonical form factor used on 1980s/1990s VME adapter boards, where socket replacement remains practical. The 5V ±5% supply rails directly from the VMEbus backplane, eliminating the need for additional level shifting. The 12 dedicated inputs accept VMEbus address lines without contention, while the 24 bidirectional I/O pins serve DTACK, IACK, BBSY, and peripheral-control functions.
Recomendado
Multibus I Glue-Logic Consolidation
The EP910DC-35 fits Multibus I glue-logic consolidation because it can replace 6-10 standard SSI/MSI 74LS/74FTTL packages (PALs, latches, transceivers, flip-flops) with a single programmable device, simplifying board layout and improving reliability. With 24 macrocells, 36 inputs and 240 product terms, the part handles Multibus I control-signal generation (MWTC, MRDC, IORC, IOWC, XACK, BCLK/2) along with auxiliary status/control logic. The 35 ns tpd provides adequate margin against the 100 ns Multibus I cycle time, and the ceramic DIP-40 package matches the through-hole form factor dominant on Multibus I motherboards from the 1980s. A single EP910DC-35 typically replaces an entire logic cluster of PAL16L8, PAL20L8 and 74LS244/74LS373 packages.
Recomendado
8086/80286/80386 Peripheral Controller PLD
The EP910DC-35 fits 8086-family peripheral controller designs because its 24 macrocells and 240 product terms can implement DMA controller glue, wait-state generators, interrupt controllers (8259A-like), bus arbiter and chip-select decoder logic in one device. With a 35 ns tpd, the EP910DC-35 adds less than one 8 MHz 8086 clock period of propagation delay, easily fitting the 125 ns minimum bus-cycle time. The 5V ±5% supply matches the iAPX-86 power rail directly, and the 40-pin CDIP ceramic package is the industry-standard form factor for industrial single-board computers of that era. Engineers often program the EP910DC-35 as a 'system PLD' that consolidates the entire peripheral-control logic cluster on industrial PC/104 and STD-bus boards.
Recomendado
Industrial State-Machine Controller
The EP910DC-35 fits industrial state-machine controller applications because all 24 macrocells can be configured as D/T/JK flip-flops, providing a 24-state registered state machine that can sequence complex machinery operations (conveyor, packaging, pick-and-place). The 240 product terms drive state-transition logic with up to 36 inputs (12 dedicated + 24 bidirectional) for sensor inputs, limit switches, encoder feedback and operator-panel buttons. The commercial 0°C to 70°C range covers most factory-floor environments when housed in a sealed enclosure, and the 35 ns tpd supports state-transition rates up to ~28 MHz, well above any electromechanical process. The through-hole CDIP-40 package withstands industrial vibration better than fine-pitch SMT alternatives, making the EP910DC-35 a preferred choice for legacy factory-automation retrofits.
Recomendado
Vintage PAL Cluster Replacement
The EP910DC-35 fits vintage PAL-cluster replacement scenarios because it offers 240 product terms versus the typical 64-128 product terms of a single PAL20L8/PAL22V10, replacing 2-4 PAL chips and their associated 74LS244/74LS373 latches with a single EP910DC-35. Its JEDEC fuse-map format is compatible with standard 1990s PLD compilers (ABEL, CUPL, PALASM), so legacy fuse-map files can often be recompiled directly to the EP910DC-35 macrocell architecture with minimal redesign. The CDIP-40 ceramic package fits existing 40-pin socket footprints, allowing in-place upgrade from a multi-PAL board to a single EP910DC-35 design without PCB rework. This application is especially common in legacy telecom, military and aerospace systems where form-fit-function replacement is mandated.
Recomendado
Prototype and Development Platform
The EP910DC-35 fits prototype and development platforms because the ceramic CDIP-40 package includes a UV-transparent quartz window that allows the EPROM cells to be erased and reprogrammed during iterative design cycles - typically 20-30 minutes of UV exposure resets the device for re-programming. The 1000-cycle erase/program endurance rating supports full development lifecycles, and the standard JEDEC fuse-map format is readable by every commercial PLD programmer from Data I/O, BP Microsystems, HiLo and Xeltek. Universities teaching digital-logic design courses favor the EP910DC-35 (or its plastic EP910PC-35 sibling) because students can implement complete 24-bit processors and controllers in a single laboratory device, see real silicon behavior, and physically erase and re-program between lab sessions.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EP910DC-35 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EP910DC-30 | EP910PC-35 | EP910LC-35 |
|---|---|---|---|---|
| Brand | Altera (Classic EPLD) | Altera (Classic EPLD) | Altera (Classic EPLD) | Altera (Classic EPLD, low power) |
| Package | CDIP-40 (Ceramic DIP, UV window) | CDIP-40 - same | PDIP-40 (plastic, no window) | CDIP-40 - same |
| Propagation Delay (tpd) | 35 ns | 30 ns | 35 ns | 35 ns |
| Macrocells | 24 | 24 | 24 | 24 |
| Product Terms | 240 | 240 | 240 | 240 |
| Usable Gates | 900 | 900 | 900 | 900 |
| Supply Voltage | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V (lower Icc) |
| Programming Method | UV erasable | UV erasable | One-Time-Programmable (OTP) | UV erasable (low power) |
| Operating Temperature | 0°C to 70°C (commercial) | 0°C to 70°C | 0°C to 70°C | 0°C to 70°C |
| Unit Price (qty 1, as of 2026-09-10) | USD 18.50 | USD 14.20 (estimated) | USD 9.80 (estimated) | USD 22.00 (estimated, low-power premium) |
Principais diferenciais
- Highest density Classic EPLD with quartz window in CDIP-40 (vs EP610DC-35)
- UV-erasable development variant (vs EP910PC-35 (plastic OTP))
- 35 ns speed grade vs faster variants (vs EP910DC-30 (30 ns tpd))
Notas de projeto
Estimated: The EP910DC-35 draws approximately 80-120 mA Icc at 5V Vcc across the commercial temperature range when all 24 macrocells are switching at maximum toggle rate. Designers must supply Vcc on pins 38, 39 and 40 simultaneously (all three are Vcc) and connect pin 37 to ground - the datasheet requires both Vcc and GND to be connected to all three Vcc pins even if only one is used to carry current, to maintain internal substrate biasing. A 0.1 µF ceramic decoupling capacitor must be placed within 5 mm of each Vcc pin pair (38-37 and 39-40) to suppress switching transients on the 5V rail during macrocell transitions.
Critical: the EP910DC-35 in ceramic DIP-40 form requires UV erasure before re-programming - it cannot be electrically re-programmed in-circuit like a CPLD or flash-based PLD. Attempting to erase with sunlight, fluorescent office lighting or sunlight through a window is too slow (weeks); only a calibrated short-wave UV eraser at 12,000 µW/cm² will erase within 20-30 minutes. Also note: the EP910DC-35 does NOT have a JTAG or IEEE 1532 interface - programming must be done in a device programmer with a 40-pin DIP adapter. Mixing up EP910DC (windowed) with EP910PC (plastic OTP) on a development board will prevent erase cycles from working as expected.
Estimated: When laying out a 40-pin DIP footprint for EP910DC-35, the standard 0.100-inch (2.54 mm) row-to-row pitch and 0.300-inch (7.62 mm) row spacing should be used. Place a 40-pin machined-pin socket (e.g., Aries 40-6518-10 or similar) rather than soldering the ceramic DIP directly - this allows UV erasure and re-programming during development without desoldering the device. Keep all high-speed signals (clock, output enables) on shorter traces (< 50 mm) to preserve 35 ns timing margins; longer traces add propagation delay that can violate worst-case timing when the part is operated at the upper end of its 37 MHz fmax rating.
Informações de conformidade
Ceramic DIP-40 with Pb-bearing lead finish; designed pre-RoHS (2006). Not AEC-Q100 qualified (commercial temp grade only). REACH and conflict-mineral declarations not available for this obsolete part.
