EPC1LC20-W - 1Mb OTP Configuration PROM 20-PLCC | Intel/Altera
N.º da peça: EPC1LC20-W ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.75 | $1.375,00 |
| 500 | $11.4 | $5.700,00 |
| 1.000 | $9.85 | $9.850,00 |
EPC1LC20-W Visão geral
A configuration PROM is a non-volatile serial memory whose sole purpose is to boot an SRAM-based FPGA. Because SRAM cells lose their configuration when power is removed, every Altera SRAM FPGA requires an external boot source on each power-up. EPC1LC20-W fills that role by storing the FPGA's compressed bitstream and clocking it out serially to the FPGA's nCONFIG / DATA / DCLK pins, eliminating the need for a separate microcontroller boot loader.
Key features include 1 Mbit of OTP storage organized as a single daisy-chainable serial device, 8 MHz maximum configuration clock, 3.3 V and 5.0 V tolerant I/O, an integrated IEEE 1149.1 JTAG state machine for ISP, and daisy-chain support that lets multiple EPC1 / EPC2 devices cascade to program FPGAs of larger bitstream size. The 20-pin PLCC (9x9 mm) package is socket-compatible with the standard EPC1LC20 footprint and is JEDEC standard.
Architecturally, the EPC1LC20-W contains an OTP memory array, an oscillator / DCLK generator, a JTAG TAP controller, and a serial configuration state machine. The internal oscillator drives DCLK to the FPGA during configuration, while DATA shifts out the bitstream. Because configuration is one-time, the part cannot be re-programmed in-circuit through JTAG - ISP only writes, never erases, the OTP array.
Typical applications include standalone FPGA boot for Altera Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K and Mercury device families, industrial control cards, telecom line cards, and prototype / production systems where a discrete microcontroller boot loader is undesirable. Designers often pair it with EPC2 LC20 (re-programmable variant) during development and migrate to EPC1LC20-W in volume.
When designing with this part, observe the nCONFIG / nSTATUS timing relationships specified in the Altera Configuration Devices handbook and ensure the 20-PLCC socket is rated for the operating temperature range. The -W (lead-free) finish is fully backward-compatible with the standard EPC1LC20 footprint.
Alternativas drop-in para EPC1LC20-W — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPC1LC20-W (mesmo formato e footprint) — diferindo em Package, Memory Type, Mounting Type, Compatible FPGA Families, Interface.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
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Ver ficha técnica →EPC1LC20-W Classificações máximas e características elétricas
| Tipo de memória | OTP (One-Time Programmable) Configuration PROM |
| Tamanho da memória | 1 Mbit |
| Configuration Clock (DCLK) | 8 MHz maximum |
| Tensão de alimentação | 3.3 V and 5.0 V |
| Interface | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| In-System Programming | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Encapsulamento | 20-PLCC J-lead (9x9 mm) |
| Lead Finish | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | Yes - stores compressed Altera FPGA bitstreams |
| Programming Cycles | 1 (OTP) |
| Target FPGA Families | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |
| Status RoHS | Compliant (Pb-free -W finish) |
| Tipo de montagem | Surface Mount (PLCC socket or direct solder) |
Configuração de pinos do EPC1LC20-W
| Pino 1 | DATA — Serial configuration data output to FPGA DATA pin |
| Pino 2 | DCLK — Configuration clock output to FPGA DCLK pin |
| Pino 3 | nCONFIG — Configuration control input from FPGA / system reset logic |
| Pino 4 | nSTATUS — Configuration status bidirectional with FPGA |
| Pino 5 | CONF_DONE — Configuration-done indicator to FPGA |
| Pino 6 | nCE — Chip enable (active low) for cascade control |
| Pino 7 | nCASC — Cascade output to next EPC device in daisy chain |
| Pino 8 | GND — Ground |
| Pino 9 | VCC — Supply voltage (3.3 V or 5.0 V) |
| Pino 10 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Pino 11 | TMS — JTAG Test Mode Select |
| Pino 12 | TCK — JTAG Test Clock |
| Pino 13 | TDO — JTAG Test Data Out |
| Pino 14 | OE — Output enable (active low) |
| Pino 15 | RESERVED — Reserved - leave open or tie to VCC per datasheet |
| Pino 16 | RESERVED — Reserved - leave open or tie to VCC per datasheet |
| Pino 17 | RESERVED — Reserved - leave open or tie to VCC per datasheet |
| Pino 18 | RESERVED — Reserved - leave open or tie to VCC per datasheet |
| Pino 19 | RESERVED — Reserved - leave open or tie to VCC per datasheet |
| Pino 20 | RESERVED — Reserved - leave open or tie to VCC per datasheet |
Aplicações típicas
EPC1LC20-W é adequado para 7 aplicaçãos: Cyclone Series FPGA Boot, FLEX 10K / 10KE / 6000 FPGA Configuration, ACEX 1K FPGA Boot, APEX 20K / Mercury Configuration, Industrial Control Card FPGA Subsystem, Telecom Line Card Boot, Prototype / Development Board FPGA Boot.
Cyclone Series FPGA Boot
The EPC1LC20-W stores the compressed configuration bitstream for Altera Cyclone (I / II / III) FPGAs and clocks it out serially at up to 8 MHz DCLK on power-up. Cyclone densities below ~250 K LE fit comfortably in the 1-Mbit capacity when bitstream compression is enabled in Quartus. The 20-PLCC footprint and 3.3 V tolerance align with Cyclone's 3.3 V VCCIO, and the JTAG ISP port allows factory programming without an external programmer. Compared with discrete microcontroller boot, the EPC1LC20-W reduces BOM cost, frees the MCU for application tasks, and guarantees deterministic configuration timing because DCLK is generated internally by the PROM rather than software.
Recomendado
FLEX 10K / 10KE / 6000 FPGA Configuration
The EPC1LC20-W is the canonical Altera-recommended boot PROM for FLEX 6000, FLEX 10K, and FLEX 10KE SRAM FPGAs. With 1 Mbit of OTP storage, it can hold the bitstream for many FLEX 10K density points (EPF10K10, EPF10K20, EPF10K30, EPF10K40, EPF10K50) when compression is on, and supports daisy-chaining with additional EPC devices for larger designs. The 5.0 V VCC tolerance of the EPC1LC20-W matches the FLEX 10K family which operates from 5.0 V, and the JTAG ISP enables board-level programming without removing the device. The -W (Pb-free) finish ensures RoHS compliance for industrial and consumer designs.
Recomendado
ACEX 1K FPGA Boot
The EPC1LC20-W can boot ACEX 1K (EP1K10, EP1K30, EP1K50, EP1K100) SRAM FPGAs by storing their compressed bitstream and clocking it out via DCLK/DATA on power-up. ACEX 1K uses the same serial configuration protocol as FLEX 10K, making the EPC1LC20-W electrically and timing-compatible without any glue logic. The 20-PLCC J-lead package fits the ACEX evaluation board socket pattern, and the JTAG ISP allows in-system programming during prototype bring-up. For ACEX 1K100 designs that exceed 1 Mbit after compression, daisy-chain two EPC1 devices in series.
Recomendado
APEX 20K / Mercury Configuration
The EPC1LC20-W supports configuration of APEX 20K (EP20K100, EP20K200) and Mercury (EP1M120) device families through the same daisy-chain serial protocol. Because these FPGAs are large, the 1-Mbit capacity is generally only sufficient with bitstream compression enabled in Quartus; otherwise multiple EPC1 / EPC2 devices must be cascaded. The EPC1LC20-W's 8 MHz DCLK keeps configuration time under 200 ms for typical APEX 20K designs, and the JTAG ISP lets production boards be programmed after PCB assembly without reworking the part.
Recomendado
Industrial Control Card FPGA Subsystem
Industrial control cards use SRAM FPGAs for high-speed logic, motor control, or signal processing, and the EPC1LC20-W provides a compact Pb-free 20-PLCC boot source that meets industrial temperature and RoHS requirements. The 3.3 V / 5.0 V tolerance allows direct connection to either 5 V legacy logic or 3.3 V modern FPGA banks. The OTP nature of the EPC1LC20-W guarantees that the configuration is locked at production - a security feature for industrial OEMs concerned about field-tampering. Combined with a watchdog MCU, the subsystem becomes a deterministic control platform.
Recomendado
Telecom Line Card Boot
Telecom line cards frequently integrate Altera FPGAs for packet processing, and the EPC1LC20-W provides a Pb-free 20-PLCC boot source that survives solder reflow profiles required for telecom-grade PCB assembly. The 8 MHz DCLK enables sub-second configuration, important for warm-swappable line cards that must come online quickly after insertion. Multiple EPC1 devices can daisy-chain to boot large FPGAs in central-office backplane applications. For designs that require field firmware updates, the EPC2LC20 in the same 20-PLCC footprint is the recommended companion during development.
Recomendado
Prototype / Development Board FPGA Boot
Development kits for Cyclone, FLEX, ACEX and APEX families use the EPC1LC20-W as the on-board configuration source so designers can quickly boot reference designs without writing a custom boot loader. The 20-PLCC socket on most Altera dev boards accepts both the EPC1LC20 (OTP) and EPC2LC20 (re-programmable) interchangeably, allowing developers to swap parts between prototype (re-programmable) and production (OTP) phases. The JTAG ISP header on the dev board connects directly to the EPC1LC20-W's TDI / TDO / TMS / TCK pins.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPC1LC20-W — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPC1LC20 | EPC2LC20 | EPC1L20 | EPC1441LC20 | EPC144LC20 |
|---|---|---|---|---|---|---|
| Brand | Intel / Altera | Intel / Altera (same) | Intel / Altera (same) | Intel / Altera (same) | Intel / Altera (same) | Intel / Altera (same) |
| Package | 20-PLCC (J-lead, 9x9 mm) | 20-PLCC - same | 20-PLCC - same | 20-PLCC - same | 20-PLCC - same | 20-PLCC - same |
| Memory Type | OTP (one-time programmable) | OTP | Flash (re-programmable) | OTP | OTP | OTP |
| Memory Size | 1 Mbit | 1 Mbit | 1.6 Mbit | 1 Mbit | 1.6 Mbit | 1 Mbit |
| DCLK Maximum | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz |
| Supply Voltage | 3.3 V / 5.0 V | 3.3 V / 5.0 V | 3.3 V / 5.0 V | 3.3 V / 5.0 V | 3.3 V / 5.0 V | 3.3 V / 5.0 V |
| Programming Interface | JTAG (IEEE 1149.1) ISP, write-only OTP | JTAG ISP, write-only OTP | JTAG ISP, multi-cycle flash | JTAG ISP, write-only OTP | JTAG ISP, write-only OTP | JTAG ISP, write-only OTP |
| Lead Finish | Pb-free (matte tin) - "-W" | SnPb (non-W) | Pb-free | Pb-free | SnPb | SnPb |
| Daisy-Chain Capable | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Obsolete (stock only) | Obsolete | Obsolete / NRND | Obsolete | Obsolete | Obsolete |
Principais diferenciais
- Pb-free lead finish on identical 20-PLCC footprint (vs EPC1LC20 (SnPb finish))
- Drop-in OTP replacement compatible with re-programmable EPC2LC20 socket (vs EPC2LC20 (flash))
- Same 20-PLCC footprint across the EPC144 / EPC1441 family (vs EPC1441LC20 (1.6 Mbit))
Notas de projeto
The EPC1LC20-W operates from 3.3 V or 5.0 V VCC. Decouple VCC (pin 9) with a 100 nF ceramic capacitor placed within 5 mm of the PLCC pin, plus a 10 uF tantalum or ceramic bulk capacitor on the same VCC node. During configuration the PROM draws brief current pulses on DCLK transitions - keep the VCC trace wide enough to maintain regulation. If powering the FPGA and PROM from the same 3.3 V rail, ensure the upstream LDO can source the combined inrush.
Do not assume EPC1LC20-W can be re-programmed via JTAG. The device is OTP: the JTAG TAP can write the bitstream once, but cannot erase or rewrite the array. Attempting repeated writes will fail or corrupt the existing bitstream. For development / field update workflows, swap to EPC2LC20 (flash-based, hundreds of cycles) which is pin-compatible in the same 20-PLCC socket.
The 20-PLCC J-lead package should be either socketed (for production flexibility) or soldered directly with a reflow profile compatible with matte-tin lead-free finish. Follow JEDEC J-STD-020 for Pb-free reflow, with a peak body temperature of 245-250 C for ~30 seconds above 217 C. Reserve a JTAG header (TDI / TMS / TCK / TDO / GND) on the PCB to enable factory ISP of the EPC1LC20-W without removing the part.
Informações de conformidade
Pb-free lead finish (-W suffix) per Altera product documentation. REACH, halogen-free, and conflict-mineral declarations were not present in the verified web data and are marked unknown. AEC-Q100 not applicable for this legacy configuration PROM.
