EPM3512ATI256-10N vs EPM3512AFI256-10N Comparação
Comparação detalhada lado a lado de EPM3512ATI256-10N por Intel e EPM3512AFI256-10N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ Última compraComparação de especificações
| Parâmetro | EPM3512ATI256-10N | EPM3512AFI256-10N |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Última compra |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $19,85 | $21,75 |
| Manufacturer | Intel (formerly Altera Corporation) | — |
| Family | MAX 3000A | MAX 3000A |
| Device | EPM3512A | — |
| Macrocells | 512 | — |
| Usable Gates | 10,000 | Up to 10,000 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O | 212 | — |
| Speed Grade | -10 (10 ns pin-to-pin delay) | -10 (10 ns tPD) |
| Encapsulamento | 256-pin BGA (TI256) | 256-ball FineLine BGA (FBGA-256) |
| Temperatura de operação | -40C to +85C (Industrial) | — |
| Core Voltage | 3.3 V | — |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Programming Technology | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | IEEE Std 1149.1 boundary-scan, 4-pin JTAG | — |
| Programmable Security Bit | Yes (design protection) | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Status do ciclo de vida | Obsolete / Last Time Buy (per Altera product discontinuation notices) | — |
| Series | — | EPM3512 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | CMOS EEPROM-based, MAX architecture |
| Number of Macrocells | — | 512 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Number of User I/O | — | 208 |
| Total Pins | — | 256 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Core Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Supply Voltage (VCCIO) | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| MultiVolt I/O Support | — | 5.0 V / 3.3 V / 2.5 V |
| In-System Programmability | — | Yes - IEEE Std 1532 compliant |
| JTAG Boundary Scan | — | Yes - IEEE 1149.1 |
| Program Memory | — | EEPROM (non-volatile) |
| Faixa de temperatura de operação | — | -40 °C to +85 °C (industrial) |