EPM3512ATI256-10N vs EPM3512AFI256-10N 对比

详细并排对比 EPM3512ATI256-10N 出自 Intel 和 EPM3512AFI256-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3512AFI256-10N EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera

EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera

EPM3512AFI256-10N ⚠ 最后一次采购

规格对比

参数 EPM3512ATI256-10N EPM3512AFI256-10N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $19.85 $21.75
Manufacturer Intel (formerly Altera Corporation) —
Family MAX 3000A MAX 3000A
Device EPM3512A —
Macrocells 512 —
Usable Gates 10,000 Up to 10,000
Logic Array Blocks (LABs) 16 —
Maximum User I/O 212 —
Speed Grade -10 (10 ns pin-to-pin delay) -10 (10 ns tPD)
封装 256-pin BGA (TI256) 256-ball FineLine BGA (FBGA-256)
工作温度 -40C to +85C (Industrial) —
Core Voltage 3.3 V —
I/O Voltage Support 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) —
Programming Technology EEPROM (non-volatile, in-system programmable) —
JTAG Support IEEE Std 1149.1 boundary-scan, 4-pin JTAG —
Programmable Security Bit Yes (design protection) —
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status] Compliant
生命周期状态 Obsolete / Last Time Buy (per Altera product discontinuation notices) —
Series — EPM3512
Device Type — CPLD (Complex Programmable Logic Device)
Architecture — CMOS EEPROM-based, MAX architecture
Number of Macrocells — 512
Number of Logic Array Blocks (LABs) — 16
Number of User I/O — 208
Total Pins — 256
Pin-to-Pin Propagation Delay (tPD) — 10 ns
Maximum Counter Frequency — 227.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
I/O Supply Voltage (VCCIO) — 2.5 V or 3.3 V (5.0 V tolerant inputs)
MultiVolt I/O Support — 5.0 V / 3.3 V / 2.5 V
In-System Programmability — Yes - IEEE Std 1532 compliant
JTAG Boundary Scan — Yes - IEEE 1149.1
Program Memory — EEPROM (non-volatile)
工作温度范围 — -40 °C to +85 °C (industrial)

数据手册与资源

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