EPM5192AJI84-15 vs EPM5192ALC84-15 Comparação
Comparação detalhada lado a lado de EPM5192AJI84-15 por Altera e EPM5192ALC84-15 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM5192AJI84-15 | EPM5192ALC84-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $27,80 | $13,20 |
| Device Family | MAX 5000 EPLD | MAX 5000 (EPM5192) |
| Product Type | UV-Erasable / OTP Complex PLD | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 84 | 64 |
| Propagation Delay (tPD) | 15 ns | 15 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | 4.75 V to 5.25 V (nominal 5 V) |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS (EPROM-based) |
| Package Type | 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window | — |
| Tipo de montagem | Through-Hole (SMD socket-compatible) | — |
| Temperatura de operação | -40 °C to +85 °C (Industrial, 'I' suffix) | — |
| Programming Method | UV erase + EPROM program via standard Altera programmer | — |
| Design Tool Support | MAX+PLUS II (legacy); not supported by modern Quartus Prime | — |
| Status RoHS | unknown | — |
| Lead-Free | unknown | — |
| Livre de halogênio | unknown | — |
| Functional Equivalent (Plastic OTP) | EPM5192AJC84-15 (windowless plastic JLCC, same die) | — |
| Device Type | — | CPLD / UV-Erasable / OTP Complex PLD |
| Dedicated Inputs | — | 7 |
| Propagation Delay (Industry Variant) | — | 25 ns (per MicrochipUSA listing) |
| Programmability | — | UV-erasable window / OTP |
| Encapsulamento | — | 84-pin PLCC (QCCJ, J-bend ceramic) |
| Operating Temperature Grade | — | Commercial |
| Terminal Form | — | J-BEND |
| Package Code | — | QCCJ |
| Package Shape | — | SQUARE |
| Architecture | — | Programmable Logic Array + Macrocell Registers + PIA interconnect |