EPM5192AJI84-15 vs EPM5192ALC84-15 비교

다음의 상세 나란히 비교: EPM5192AJI84-15 제조: Altera 및 EPM5192ALC84-15 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5192AJI84-15 EPM5192ALC84-15
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $27.80 $13.20
Device Family MAX 5000 EPLD MAX 5000 (EPM5192)
Product Type UV-Erasable / OTP Complex PLD —
Macrocells 192 192
Logic Array Blocks (LABs) 16 —
User I/O Pins 84 64
Propagation Delay (tPD) 15 ns 15 ns
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) 4.75 V to 5.25 V (nominal 5 V)
Process Technology CMOS EPROM (UV-erasable) CMOS (EPROM-based)
Package Type 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window —
실장 유형 Through-Hole (SMD socket-compatible) —
동작 온도 -40 °C to +85 °C (Industrial, 'I' suffix) —
Programming Method UV erase + EPROM program via standard Altera programmer —
Design Tool Support MAX+PLUS II (legacy); not supported by modern Quartus Prime —
RoHS 상태 unknown —
Lead-Free unknown —
할로겐 프리 unknown —
Functional Equivalent (Plastic OTP) EPM5192AJC84-15 (windowless plastic JLCC, same die) —
Device Type — CPLD / UV-Erasable / OTP Complex PLD
Dedicated Inputs — 7
Propagation Delay (Industry Variant) — 25 ns (per MicrochipUSA listing)
Programmability — UV-erasable window / OTP
패키지 — 84-pin PLCC (QCCJ, J-bend ceramic)
Operating Temperature Grade — Commercial
Terminal Form — J-BEND
Package Code — QCCJ
Package Shape — SQUARE
Architecture — Programmable Logic Array + Macrocell Registers + PIA interconnect

데이터시트 & 자료

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