EPM9320LC84-20N vs EPM9320LC84-15 Comparação
Comparação detalhada lado a lado de EPM9320LC84-20N por Intel e EPM9320LC84-15 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM9320LC84-20N | EPM9320LC84-15 |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $10,25 | $17,95 |
| Series | MAX 9000 | EPM9320 |
| Logic Family | CMOS (EEPROM-based) | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Número de pinos | 84 | — |
| Package Type | Plastic Leaded Chip Carrier (PLCC-84, J-bend) | — |
| Package Code | QCCJ | — |
| Propagation Delay (tPD) | 16 ns | 15 ns (max) |
| Internal Frequency | 118 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5.0 V nominal) |
| Temperatura de operação | 0 C to +70 C (Commercial) | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Programming | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) | — |
| Tipo de montagem | Surface Mount (J-bend) | Surface Mount |
| Terminal Form | J BEND | — |
| Nível MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: confirm from manufacturer] |
| Family | — | MAX 9000 |
| Logic Array Blocks (LABs) | — | 20 |
| Frequência máxima de clock | — | 117.6 MHz |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Encapsulamento | — | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |