RTAX1000SL-CGS624E vs RTAX1000SL-1CGS624V Comparação

Comparação detalhada lado a lado de RTAX1000SL-CGS624E por Microchip Technology e RTAX1000SL-1CGS624V por Microchip Technology. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Microchip Technology
RTAX1000SL-CGS624E RTAX1000SL-CGS624E - 1M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip

RTAX1000SL-CGS624E - 1M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip

RTAX1000SL-CGS624E ✓ Ativo
Microchip Technology
RTAX1000SL-1CGS624V RTAX1000SL-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000SL-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000SL-1CGS624V ✓ Ativo

Comparação de especificações

Parâmetro RTAX1000SL-CGS624E RTAX1000SL-1CGS624V
Marca Microchip Technology Microchip Technology
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Ativo Ativo
Status do estoque In Stock In Stock
Preço unitário (USD) $3.970,00 $1,00
Equivalent System Gates 1000000 gates —
Additional ASIC Gates 125000 gates —
Configurable Logic Blocks (CLBs) 12096 —
Maximum System Frequency 581 MHz —
Process Technology 0.15 um CMOS —
Core Supply Voltage 1.5 V —
Family RTAX-S/SL Radiation-Tolerant FPGA —
Encapsulamento 624-ball Ceramic Column Grid Array (CGS624) —
Radiation Tolerance Radiation-tolerant (space-flight qualified family) Radiation-tolerant (space-flight qualified family)
Configuration Non-volatile anti-fuse, live-at-power-up, single chip Live at power-up, single chip, no external boot PROM
Embedded Memory Embedded SRAM with built-in FIFO control logic Embedded SRAM with built-in FIFO control logic
Clocking Features Segmentable clocks, chip-wide highway routing —
Arithmetic Support Dedicated carry logic —
Tipo de montagem Surface Mount Surface Mount
Temperatura de operação [DATA_NEEDED: Operating Temperature] -55C to +125C
I/O Count [DATA_NEEDED: User I/O Count] —
Status RoHS [DATA_NEEDED: RoHS Status] [DATA_NEEDED: RoHS status]
System Gates — 1,000,000 (1.00E6)
Logic Cells / Logic Blocks — 12096
Logic Family — Digital CMOS
Programmable Technology — Antifuse (one-time programmable)
Package Type — CGA-624 (ceramic column grid array)
Contagem de pinos — 624
Speed Grade — -1 (standard)
SEU Immunity — SEU-hardened registers; SEU rate < 10-10 errors/bit-day
Clocking — Segmentable clock resources
Routing Features — Chip-wide highway routing, carry logic
Tensão de alimentação — [DATA_NEEDED: core/IO supply voltage]

Fichas técnicas e recursos

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