RTAX1000SL-CGS624E vs RTAX1000SL-1CGS624V 비교

다음의 상세 나란히 비교: RTAX1000SL-CGS624E 제조: Microchip Technology 및 RTAX1000SL-1CGS624V 제조: Microchip Technology. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

Microchip Technology
RTAX1000SL-CGS624E RTAX1000SL-CGS624E - 1M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip

RTAX1000SL-CGS624E - 1M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip

RTAX1000SL-CGS624E ✓ 활성
Microchip Technology
RTAX1000SL-1CGS624V RTAX1000SL-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000SL-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000SL-1CGS624V ✓ 활성

사양 비교

파라미터 RTAX1000SL-CGS624E RTAX1000SL-1CGS624V
브랜드 Microchip Technology Microchip Technology
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 활성 활성
재고 상태 In Stock In Stock
단가 (USD) $3,970.00 $1.00
Equivalent System Gates 1000000 gates —
Additional ASIC Gates 125000 gates —
Configurable Logic Blocks (CLBs) 12096 —
Maximum System Frequency 581 MHz —
Process Technology 0.15 um CMOS —
Core Supply Voltage 1.5 V —
Family RTAX-S/SL Radiation-Tolerant FPGA —
패키지 624-ball Ceramic Column Grid Array (CGS624) —
Radiation Tolerance Radiation-tolerant (space-flight qualified family) Radiation-tolerant (space-flight qualified family)
Configuration Non-volatile anti-fuse, live-at-power-up, single chip Live at power-up, single chip, no external boot PROM
Embedded Memory Embedded SRAM with built-in FIFO control logic Embedded SRAM with built-in FIFO control logic
Clocking Features Segmentable clocks, chip-wide highway routing —
Arithmetic Support Dedicated carry logic —
실장 유형 Surface Mount Surface Mount
동작 온도 [DATA_NEEDED: Operating Temperature] -55C to +125C
I/O Count [DATA_NEEDED: User I/O Count] —
RoHS 상태 [DATA_NEEDED: RoHS Status] [DATA_NEEDED: RoHS status]
System Gates — 1,000,000 (1.00E6)
Logic Cells / Logic Blocks — 12096
Logic Family — Digital CMOS
Programmable Technology — Antifuse (one-time programmable)
Package Type — CGA-624 (ceramic column grid array)
핀 수 — 624
Speed Grade — -1 (standard)
SEU Immunity — SEU-hardened registers; SEU rate < 10-10 errors/bit-day
Clocking — Segmentable clock resources
Routing Features — Chip-wide highway routing, carry logic
공급 전압 — [DATA_NEEDED: core/IO supply voltage]

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