XC3090L-8PCG84C vs XC3090L-8PC84BKJ Comparação
Comparação detalhada lado a lado de XC3090L-8PCG84C por Xilinx e XC3090L-8PC84BKJ por Xilinx. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | XC3090L-8PCG84C | XC3090L-8PC84BKJ |
|---|---|---|
| Marca | Xilinx | Xilinx |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Última compra | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $26,10 | $19,20 |
| Family | XC3000A/L Series FPGA | XC3000L Low-Voltage Logic Cell Array |
| Logic Cells / CLBs | 70 Configurable Logic Blocks | — |
| Gate Count | 6,400 gates (typical) | — |
| Configuration Program Store | 64,160 bits | — |
| User I/O Pins | 70 (maximum) | — |
| Encapsulamento | 84-pin PLCC (J-Lead, PCG84) | 84-pin PLCC (J-Lead), windowed ceramic (BKJ) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (low-voltage 'L' variant) | — |
| Speed Grade | -8 (moderate) | -8 (approx. 70 MHz toggle) |
| Temperatura de operação | 0 C to +70 C (commercial 'C' suffix) | 0C to +70C (commercial, C suffix) |
| Configuration Modes | Serial master/slave, parallel master/slave, peripheral mode | — |
| Process Technology | [DATA_NEEDED: process node] | 5 ns CMOS SRAM |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Configuration Clock Range | [DATA_NEEDED: CCLK frequency range] | — |
| Tipo de montagem | Surface Mount (PLCC J-Lead) | Through-hole (PLCC socket) |
| Status RoHS | unknown | unknown - legacy windowed ceramic package |
| Lead-Free | unknown | — |
| Nível MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Programming Technology | SRAM-based, in-system reconfigurable | — |
| Logic Cells | — | 320 |
| Usable Gates | — | 6,000 |
| Configuration Memory | — | 64,160 bits |
| Maximum User I/O | — | 144 |
| Supply Voltage (Vcc) | — | 3.0 V to 3.6 V (low-voltage) |
| Configuration Method | — | Serial/parallel SRAM, in-system reconfigurable |
| Boundary Scan | — | IEEE 1149.1 (JTAG) compliant |
| Configuration Pins | — | M0, M1, M2 mode-select + DIN, DOUT, CCLK, INIT |