XC3090L-8PCG84C vs XC3090L-8PC84BKJ Comparaison
Comparaison détaillée côte à côte de XC3090L-8PCG84C par Xilinx et XC3090L-8PC84BKJ par Xilinx. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC3090L-8PCG84C | XC3090L-8PC84BKJ |
|---|---|---|
| Marque | Xilinx | Xilinx |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $26,10 | $19,20 |
| Family | XC3000A/L Series FPGA | XC3000L Low-Voltage Logic Cell Array |
| Logic Cells / CLBs | 70 Configurable Logic Blocks | — |
| Gate Count | 6,400 gates (typical) | — |
| Configuration Program Store | 64,160 bits | — |
| User I/O Pins | 70 (maximum) | — |
| Boîtier | 84-pin PLCC (J-Lead, PCG84) | 84-pin PLCC (J-Lead), windowed ceramic (BKJ) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (low-voltage 'L' variant) | — |
| Speed Grade | -8 (moderate) | -8 (approx. 70 MHz toggle) |
| Température de fonctionnement | 0 C to +70 C (commercial 'C' suffix) | 0C to +70C (commercial, C suffix) |
| Configuration Modes | Serial master/slave, parallel master/slave, peripheral mode | — |
| Process Technology | [DATA_NEEDED: process node] | 5 ns CMOS SRAM |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Configuration Clock Range | [DATA_NEEDED: CCLK frequency range] | — |
| Type de montage | Surface Mount (PLCC J-Lead) | Through-hole (PLCC socket) |
| Statut RoHS | unknown | unknown - legacy windowed ceramic package |
| Lead-Free | unknown | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Programming Technology | SRAM-based, in-system reconfigurable | — |
| Logic Cells | — | 320 |
| Usable Gates | — | 6,000 |
| Configuration Memory | — | 64,160 bits |
| Maximum User I/O | — | 144 |
| Supply Voltage (Vcc) | — | 3.0 V to 3.6 V (low-voltage) |
| Configuration Method | — | Serial/parallel SRAM, in-system reconfigurable |
| Boundary Scan | — | IEEE 1149.1 (JTAG) compliant |
| Configuration Pins | — | M0, M1, M2 mode-select + DIN, DOUT, CCLK, INIT |