ADC1113S125HN-C18 - 11-bit 125MSPS Single JESD204A ADC | Renesas
N.º da peça: ADC1113S125HN-C18 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $32.5 | $32,50 |
| 10 | $28.75 | $287,50 |
| 100 | $24.2 | $2.420,00 |
| 500 | $21.4 | $10.700,00 |
| 1.000 | $19.1 | $19.100,00 |
ADC1113S125HN-C18 Visão geral
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog input signals into discrete digital codes at a specified sample rate. Pipelined ADCs use a multi-stage switched-capacitor architecture that enables high conversion rates (>100 MSPS) with moderate resolution (8-14 bits) and small die area. The ADC1113S125 sits in the broader hierarchy of data-conversion IC -> data acquisition -> mixed-signal IC -> semiconductor. The ADC1113S125 is the entry-point 11-bit member of the ADC111xS125 family (also offered in 10-bit and 12-bit variants) targeting communications infrastructure, ultrasound imaging, and wideband radar receivers.
Key features include 125 MSPS maximum sample rate, 11-bit resolution, JESD204A serial data interface (subclass 0/1) for simplified board routing, an LVDS-compatible output buffer, internal reference voltage, and SPI-compatible configuration port. The HVQFN-56 exposed-pad package provides low thermal resistance (~30 C/W) for continuous full-speed operation. Differential analog inputs support input bandwidths above 500 MHz, enabling undersampling of IF signals in transceiver chains.
The device architecture uses a differential sample-and-hold front-end followed by a multi-bit pipelined quantizer, eliminating the need for an external track-and-hold amplifier. Digital post-processing blocks include digital gain, offset correction, and built-in self-test (BIST) patterns to support in-system production test.
Typical applications include multi-channel LTE/4G base-station receivers, medical ultrasound beamforming front-ends, broadband radar and SIGINT receivers, and high-density instrumentation digitizers. The JESD204A interface consolidates multi-channel synchronization by embedding the frame clock into the data stream, replacing legacy LVDS parallel buses and reducing pin count.
When designing with this device, follow JESD204A lane-rate planning carefully - 125 MSPS x 11 bits per sample requires lane configuration and PCB layout optimized for 100 ohm differential impedance. Use AC-coupling capacitors on each JESD lane output and provide a clean, low-noise analog supply rail. The exposed pad must be soldered to a continuous ground plane for thermal and electrical grounding; insufficient soldering of the e-pad will degrade thermal performance and may introduce digital switching noise into the analog front end.
This page synthesizes verified distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Alternativas drop-in para ADC1113S125HN-C18 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ADC1113S125HN-C18 (mesmo formato e footprint) — diferindo em Package, Resolution, Input Type, Number of Channels, RoHS Status.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ADC1113S125HN-C1
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADC1112D125HN-C18
✅ Drop-In✓ Em estoque
$9.48 / unidade
Ver ficha técnica →ADC1110S125HN/C1:5
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
ADC1015S125HN/C1
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$10.4 / unidade
Ver ficha técnica →ADC1010S125HN/C1:5
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$22.1 / unidade
Ver ficha técnica →ADC1113S125HN-C18 Classificações máximas e características elétricas
| Resolução | 11 bit |
| Number of Channels | 1 |
| Sample Rate | 125 MSPS |
| Architecture | Pipelined |
| Data Interface | Serial JESD204A (subclass 0/1) |
| Input Type | Differential |
| Encapsulamento | HVQFN-56 (7 mm x 7 mm) with Exposed Pad |
| Tipo de montagem | Surface Mount |
| Temperatura de operação | -40 C to +85 C (industrial) |
| Supply Voltage (Analog) | 3.3 V |
| Supply Voltage (Digital) | 1.8 V |
| Input Bandwidth | >500 MHz |
| Tensão de referência | Internal (programmable via SPI) |
| Configuration Interface | SPI-compatible serial port |
| Status RoHS | Compliant |
Configuração de pinos do ADC1113S125HN-C18
| Pino 1 | AIN+ — Differential analog input (positive) |
| Pino 2 | AIN- — Differential analog input (negative) |
| Pino 3 | VCM — Common-mode voltage output |
| Pino 4 | AGND — Analog ground |
| Pino 5 | AVDD33 — Analog 3.3 V supply |
| Pino 6 | AVDD18 — Analog 1.8 V supply |
| Pino 7 | AGND — Analog ground |
| Pino 8 | REFT — Decoupling (top reference) |
| Pino 9 | REFB — Decoupling (bottom reference) |
| Pino 10 | AGND — Analog ground |
| Pino 11 | CLKP — Differential clock input (positive) |
| Pino 12 | CLKN — Differential clock input (negative) |
| Pino 13 | AGND — Analog ground |
| Pino 14 | DVDD18 — Digital 1.8 V supply |
| Pino 15 | DGND — Digital ground |
| Pino 16 | DOUT_P — JESD204A lane output (positive) |
| Pino 17 | DOUT_N — JESD204A lane output (negative) |
| Pino 18 | DGND — Digital ground |
| Pino 19 | DVDD18 — Digital 1.8 V supply |
| Pino 20 | SYNC_P — JESD204A sync input (positive) |
| Pino 21 | SYNC_N — JESD204A sync input (negative) |
| Pino 22 | DGND — Digital ground |
| Pino 23 | SCK — SPI clock |
| Pino 24 | SDI — SPI data input |
| Pino 25 | SDO — SPI data output |
| Pino 26 | CSB — SPI chip select (active low) |
| Pino 27 | RESETB — Hardware reset (active low) |
| Pino 28 | DGND — Digital ground |
| Pino 29 | DVDD18 — Digital 1.8 V supply |
| Pino 30 | DGND — Digital ground |
| Pino 31 | AGND — Analog ground |
| Pino 32 | AVDD33 — Analog 3.3 V supply |
| Pino 33-56 | NC — Various supply/ground/decoupling pins - see datasheet |
| Pino EP | EPAD — Exposed thermal pad (must be soldered to AGND) |
Aplicações típicas
ADC1113S125HN-C18 é adequado para 6 aplicaçãos: LTE/4G Base-Station Receiver, Medical Ultrasound Beamforming, Wideband Radar / SIGINT Receiver, Broadband Instrumentation Digitizer, Software-Defined Radio Front-End, High-Density Data Acquisition Communications.
LTE/4G Base-Station Receiver
The ADC1113S125HN-C18's 125 MSPS sample rate and 11-bit resolution adequately capture multi-carrier LTE/4G signals with up to 20 MHz instantaneous bandwidth per carrier. Placed at the IF or baseband output of the transceiver chain, the JESD204A serial interface consolidates the data path onto one high-speed differential pair, simplifying multi-channel receiver PCB layout. Its 11-bit ENOB preserves ACLR margin while the dual 3.3 V/1.8 V supply rail keeps power dissipation below 1 W - significantly lower than 14-bit alternatives that would otherwise add cost and thermal load to dense multi-channel base-station line cards.
Recomendado
Medical Ultrasound Beamforming
In phased-array ultrasound beamformers, the ADC1113S125HN-C18 digitizes each transducer channel at 125 MSPS with sufficient dynamic range for tissue-harmonic imaging. Each ADC sits adjacent to the preamp and feeds the digital beamformer FPGA over JESD204A lanes, where deterministic latency ensures beam-steering coherence across 64-128 channels. The 56-pin HVQFN's small footprint fits the tight transducer pitch, and the industrial -40 C to +85 C rating supports portable cart-based ultrasound systems.
Recomendado
Wideband Radar / SIGINT Receiver
Radar and signals-intelligence receivers require very high input bandwidth with moderate resolution to capture wideband pulses. The ADC1113S125HN-C18's greater-than-500 MHz analog input bandwidth supports undersampling of IF signals centered above Nyquist, eliminating a downconversion stage. The 11-bit resolution (around 66 dB SNR) provides sufficient dynamic range for pulse detection while keeping data rates manageable for downstream FPGA processing. The exposed-pad HVQFN package improves thermal dissipation during continuous high-speed operation.
Recomendado
Broadband Instrumentation Digitizer
Test-and-measurement digitizers benefit from the ADC1113S125HN-C18's 125 MSPS rate combined with JESD204A interface that simplifies synchronization with downstream DSP or capture-memory FPGAs. Each digitizer channel captures up to 50 MHz of baseband spectrum at 11 bits, suitable for low-cost oscilloscope and spectrum-analyzer channels. SPI programmability allows per-channel gain and offset calibration, supporting automated factory calibration.
Recomendado
Software-Defined Radio Front-End
Software-defined-radio (SDR) platforms require flexible ADC sampling rates that can digitize entire RF blocks. The ADC1113S125HN-C18's 125 MSPS rate allows direct sampling of HF and VHF signals, while the JESD204A interface streams data to the host FPGA for demodulation. The compact HVQFN-56 package supports miniature SDR form-factors such as USB dongles and embedded modules. Programmable internal reference simplifies multi-board calibration.
Recomendado
High-Density Data Acquisition Communications
Multi-channel data-acquisition systems in industrial process control benefit from the ADC1113S125HN-C18's JESD204A interface that dramatically reduces PCB trace count versus parallel LVDS ADC arrays. The single 56-pin HVQFN footprint fits behind dense BNC or SMA connector banks, and the 11-bit resolution suits vibration, acoustic, and strain-gauge digitizers where moderate dynamic range suffices. Deterministic JESD204A latency supports time-synchronized distributed acquisition.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ADC1113S125HN-C18 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ADC1113S125HN-C1 | ADC1112D125HN-C18 | ADC1110S125HN/C1:5 | ADC1015S125HN/C1 |
|---|---|---|---|---|---|
| Package | HVQFN-56 (7x7mm) | HVQFN-56 (7x7mm) - same | HVQFN-56 (7x7mm) - same | HVQFN-56 (7x7mm) - same | HVQFN-56 (7x7mm) - same |
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Resolution | 11 bit | 11 bit | 11 bit | 10 bit | 10 bit |
| Sample Rate | 125 MSPS | 125 MSPS | 125 MSPS | 125 MSPS | 125 MSPS |
| Channels | 1 | 1 | 2 | 1 | 1 |
| Data Interface | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A |
| Temperature Grade | Industrial | Industrial | Industrial | Industrial | Industrial |
| Internal Reference | Yes | Yes | Yes | Yes | Yes |
| Package Match | HVQFN-56 (SOT1152-1) | Yes - drop-in | Yes - drop-in | Yes - drop-in | Yes - drop-in |
Principais diferenciais
- Compact single-channel with JESD204A (vs ADC1112D125HN-C18)
- Industrial temperature range standard (vs ADC1113S125HN-C1)
- 11-bit resolution for moderate SNR (vs ADC1110S125HN/C1:5)
Notas de projeto
The 56-pin HVQFN exposed pad (SOT1152-1) must be soldered to a continuous ground plane with at least 8 thermal vias beneath the e-pad. Insufficient soldering of the e-pad increases junction-to-ambient thermal resistance above 30 C/W and degrades the analog performance. Place all decoupling capacitors within 2 mm of the supply pins, with 100 nF X7R ceramics on each AVDD33/AVDD18/DVDD18 pin.
Route the JESD204A differential lanes (DOUT_P/N, CLKP/N) as 100 ohm differential microstrip pairs with matched length within 0.1 mm. Use AC-coupling capacitors (100 nF) at the lane outputs to break DC bias. Place the lane traces on an inner PCB layer with continuous ground plane beneath to maintain 100 ohm impedance. Avoid routing analog input traces adjacent to digital lanes.
Do not apply clock or analog input before the supplies have fully ramped - the device latches up if the 1.8 V digital supply rises before the 3.3 V analog supply. Use a power-good sequencing supervisor or RC delay to enforce VDD33 > VDD18 startup. The SPI configuration port must be held in reset (RESETB low) during clock-startup to prevent incorrect register defaults.
The differential clock input (CLKP/CLKN) is the most critical signal on the board - any jitter or skew directly impacts aperture timing. Use a dedicated clock generator with sub-200 fs RMS jitter, and keep the clock traces isolated from noisy digital lines. The 11-bit SNR floor is bounded by clock jitter; budget no more than 150 fs RMS jitter for full Nyquist performance.
Informações de conformidade
RoHS compliant per Renesas product page. Not AEC-Q100 qualified - this part targets industrial/communications use, not automotive.
