AD9268XCPZ-125 - 16-Bit 125MSPS Dual ADC | Analog Devices
N.º da peça: AD9268XCPZ-125 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $47.5 | $47,50 |
| 10 | $42.75 | $427,50 |
| 100 | $38.2 | $3.820,00 |
| 500 | $34.1 | $17.050,00 |
| 1.000 | $30.95 | $30.950,00 |
AD9268XCPZ-125 Visão geral
An analog-to-digital converter is a mixed-signal integrated circuit that samples continuous-time analog signals and produces discrete-time digital codes at a rate determined by its sampling clock. Within the broader integrated circuit taxonomy, an ADC sits at the intersection of data acquisition ICs, signal chain components, and mixed-signal processing. The AD9268 belongs to the high-speed pipelined ADC subclass, which uses cascaded gain stages with per-stage digital error correction to achieve high sample rates while maintaining 14-to-16-bit resolution. Pipelined ADCs are the workhorse of communications, software-defined radio, medical imaging, and radar systems, where gigabit-class sample throughput is required.
Key features of the AD9268 include an internal sample-and-hold with very wide input bandwidth, an optional internal reference voltage buffer, programmable input range via the DCS pin, and pin compatibility with the 14-bit AD9258 and the lower-speed AD9251, AD9231, and AD9204 families. The differential analog inputs accept single-ended or differential drive, simplifying front-end filter design. The LVDS-compatible output data interface uses DDR clocking to halve the required output data rate per pin.
The dual ADC architecture supports I/Q sampling in direct-conversion receivers, multi-antenna diversity systems, and medical beamforming front ends. Both channels share a common sampling clock, ensuring deterministic phase alignment between the two channels - critical for coherent signal processing. The pipelined core contributes a fixed latency of approximately 14 clock cycles, which must be accounted for in synchronous system designs.
Typical applications include diversity radio receivers in cellular base stations, software-defined radio platforms, medical ultrasound imaging, portable instrumentation, and multi-channel data acquisition cards. The wide analog input bandwidth allows direct IF sampling without preceding mixer stages, simplifying the overall receiver chain.
When laying out the AD9268XCPZ-125, designers should provide a solid ground plane beneath the exposed pad, route the LVDS output pairs with controlled 100-ohm differential impedance, and decouple each supply pin with a 0.1 microfarad ceramic capacitor placed as close as possible to the package. The exposed pad must be soldered to the PCB ground for both thermal dissipation and electrical reference.
This page consolidates distributor pricing, verified drop-in alternatives, and practical PCB layout notes that supplement the manufacturer datasheet with information tailored to component selection engineers.
Alternativas drop-in para AD9268XCPZ-125 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com AD9268XCPZ-125 (mesmo formato e footprint) — diferindo em Package, Resolution, Input Type, Number of Channels, RoHS Status.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
AD9268BCPZ-125
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
AD9268XCPZ-105
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
AD9268XCPZ-80
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
AD9258XCPZ-125
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
AD9268BCPZ-105
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
AD9268XCPZ-125 Classificações máximas e características elétricas
| Resolução | 16 bit |
| Number of Channels | 2 (dual) |
| Sampling Rate (max) | 125 MSPS |
| Architecture | Pipelined |
| SNR | 78.2 dBFS @ 70 MHz input, 125 MSPS |
| SFDR | 88 dBc @ 70 MHz input, 125 MSPS |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V to 3.3 V |
| Power Dissipation | 750 mW (typ, both channels at 125 MSPS) |
| Input Type | Differential |
| Output Interface | LVDS, DDR clocking |
| Encapsulamento | 64-LFCSP-VQ (9x9 mm) with exposed pad |
| Faixa de temperatura de operação | -40C to +85C (industrial) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Internal Reference Buffer Load | 6 kOhm equivalent |
| Pin-Compatible Family | AD9258 (14-bit), AD9251, AD9231, AD9204 |
Configuração de pinos do AD9268XCPZ-125
| Pino 1 | AIN1A+ — Channel 1A positive differential analog input |
| Pino 2 | AIN1A- — Channel 1A negative differential analog input |
| Pino 3 | VCM — Common-mode voltage output for input biasing |
| Pino 4 | AIN1B+ — Channel 1B positive differential analog input |
| Pino 5 | AIN1B- — Channel 1B negative differential analog input |
| Pino 6 | REF_SEL — Internal/external reference select |
| Pino 7 | AVDD1.8 — 1.8 V analog supply |
| Pino 8 | AVDD1.8 — 1.8 V analog supply |
| Pino 9 | AGND — Analog ground |
| Pino 10 | DCS — Duty cycle stabilizer / input range select |
| Pino 11 | AGND — Analog ground |
| Pino 12 | AVDD1.8 — 1.8 V analog supply |
| Pino 13 | AVDD1.8 — 1.8 V analog supply |
| Pino 14 | SENSE — Reference mode select |
| Pino 15 | AGND — Analog ground |
| Pino 16 | VREF — Voltage reference I/O |
| Pino 17 | AGND — Analog ground |
| Pino 18 | AGND — Analog ground |
| Pino 19 | CLK+ — Differential sampling clock positive |
| Pino 20 | CLK- — Differential sampling clock negative |
| Pino 21 | AGND — Analog ground |
| Pino 22 | AVDD1.8 — 1.8 V analog supply |
| Pino 23 | AVDD1.8 — 1.8 V analog supply |
| Pino 24 | AGND — Analog ground |
| Pino 25 | AIN2A+ — Channel 2A positive differential analog input |
| Pino 26 | AIN2A- — Channel 2A negative differential analog input |
| Pino 27 | VCM — Common-mode voltage output |
| Pino 28 | AIN2B+ — Channel 2B positive differential analog input |
| Pino 29 | AIN2B- — Channel 2B negative differential analog input |
| Pino 30 | AGND — Analog ground |
| Pino 31 | AVDD1.8 — 1.8 V analog supply |
| Pino 32 | AVDD1.8 — 1.8 V analog supply |
| Pino 33 | DCO+ — DDR clock output positive |
| Pino 34 | DCO- — DDR clock output negative |
| Pino 35 | FCO+ — Frame clock output positive |
| Pino 36 | FCO- — Frame clock output negative |
| Pino 37 | D0A+ — Channel A LVDS data bit 0 positive |
| Pino 38 | D0A- — Channel A LVDS data bit 0 negative |
| Pino 39 | D1A+ — Channel A LVDS data bit 1 positive |
| Pino 40 | D1A- — Channel A LVDS data bit 1 negative |
| Pino 41 | D2A+ — Channel A LVDS data bit 2 positive |
| Pino 42 | D2A- — Channel A LVDS data bit 2 negative |
| Pino 43 | D3A+ — Channel A LVDS data bit 3 positive |
| Pino 44 | D3A- — Channel A LVDS data bit 3 negative |
| Pino 45 | D4A+ — Channel A LVDS data bit 4 positive |
| Pino 46 | D4A- — Channel A LVDS data bit 4 negative |
| Pino 47 | D5A+ — Channel A LVDS data bit 5 positive |
| Pino 48 | D5A- — Channel A LVDS data bit 5 negative |
| Pino 49 | D6A+ — Channel A LVDS data bit 6 positive |
| Pino 50 | D6A- — Channel A LVDS data bit 6 negative |
| Pino 51 | D7A+ — Channel A LVDS data bit 7 positive |
| Pino 52 | D7A- — Channel A LVDS data bit 7 negative |
| Pino 53 | DVDD — Digital supply |
| Pino 54 | DGND — Digital ground |
| Pino 55 | D0B+ — Channel B LVDS data bit 0 positive |
| Pino 56 | D0B- — Channel B LVDS data bit 0 negative |
| Pino 57 | D1B+ — Channel B LVDS data bit 1 positive |
| Pino 58 | D1B- — Channel B LVDS data bit 1 negative |
| Pino 59 | D2B+ — Channel B LVDS data bit 2 positive |
| Pino 60 | D2B- — Channel B LVDS data bit 2 negative |
| Pino 61 | D3B+ — Channel B LVDS data bit 3 positive |
| Pino 62 | D3B- — Channel B LVDS data bit 3 negative |
| Pino 63 | CSB — SPI chip select (active low) |
| Pino 64 | SCLK/SDIO — SPI serial clock / data I/O |
| Pino EP | EPAD — Exposed thermal pad, must be soldered to PCB ground |
Aplicações típicas
AD9268XCPZ-125 é adequado para 6 aplicaçãos: Diversity Cellular Base Station Receivers, Software Defined Radio Platforms, Medical Ultrasound Imaging Systems, Multi-Channel Data Acquisition Cards, Radar and Lidar Signal Processing, Portable Instrumentation and Test Equipment.
Diversity Cellular Base Station Receivers
The AD9268XCPZ-125's dual 125 MSPS 16-bit channels enable simultaneous sampling of two antenna paths in a diversity receiver. Its 78.2 dBFS SNR at 70 MHz and 88 dBc SFDR support sensitive detection of weak QPSK and 64-QAM carriers in LTE and 5G NR front ends. Per the AD9268 datasheet, the wide analog input bandwidth permits direct IF sampling, eliminating an analog mixer stage. The LVDS DDR outputs minimize the FPGA pin count for multi-antenna systems, while the 750 mW power dissipation per device stays within the thermal envelope of typical remote radio head designs.
Recomendado
Software Defined Radio Platforms
Software-defined radio benefits from the AD9268XCPZ-125's wide input bandwidth and high SFDR. With 78.2 dBFS SNR and 88 dBc spurious performance at 125 MSPS, the ADC captures wideband spectral content directly at IF, allowing a single ADC pair to cover multiple bands. Per the datasheet, the internal reference buffer simplifies the analog front end while maintaining low noise. The LVDS DDR interface connects cleanly to Xilinx and Altera FPGAs commonly used in SDR platforms, and the 64-LFCSP-VQ footprint fits within the tight board area typical of SDR modules.
Recomendado
Medical Ultrasound Imaging Systems
The AD9268XCPZ-125's dual-channel architecture suits phased-array ultrasound receivers, where each channel digitizes an element return path. At 78.2 dBFS SNR, the ADC resolves small-amplitude echoes against tissue clutter, supporting Doppler and B-mode imaging. According to the AD9268 datasheet, the deterministic pipeline latency simplifies beamforming delay calibration across channels. The 64-LFCSP-VQ 9x9 package fits inside the small probe-head electronics, and 750 mW per device fits the thermal budget of a 64-channel cart-based system.
Recomendado
Multi-Channel Data Acquisition Cards
PCIe-based data acquisition cards for instrumentation and vibration analysis leverage the AD9268XCPZ-125's dual 125 MSPS channels to double channel density without doubling board area. Per the datasheet, the LVDS DDR interface pairs cleanly with FPGA-based protocol engines, while the 78.2 dBFS SNR preserves dynamic range in spectrum analysis applications. Designers can stack multiple AD9268 devices with synchronized sampling clocks from a shared AD9516 to expand to 8 or 16 channels, all within the same 64-LFCSP-VQ footprint family.
Recomendado
Radar and Lidar Signal Processing
Phased-array radar and lidar front ends benefit from the AD9268XCPZ-125's dual channels sampling at 125 MSPS with 88 dBc SFDR. The high spurious-free dynamic range captures weak returns in the presence of strong clutter, while the deterministic pipeline latency simplifies digital beamforming. According to the AD9268 datasheet, the differential analog inputs accommodate direct coupling from bipolar front-end amplifier outputs. The compact 64-LFCSP-VQ 9x9 package fits within the size-constrained modules typical of automotive and defense radar arrays.
Recomendado
Portable Instrumentation and Test Equipment
Handheld oscilloscope and spectrum analyzer front ends use the AD9268XCPZ-125 to digitize signals up to 70 MHz bandwidth with 16-bit precision. The 78.2 dBFS SNR ensures accurate amplitude measurements, while the 88 dBc SFDR prevents spurious tones from masking small signals. Per the datasheet, the 750 mW power budget is acceptable in battery-powered instruments when paired with sleep modes via the SPI port. The 64-LFCSP-VQ 9x9 footprint enables dense PCB layouts typical of portable bench equipment.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para AD9268XCPZ-125 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | AD9268BCPZ-125 | AD9268XCPZ-105 | AD9268XCPZ-80 | AD9258XCPZ-125 | AD9268BCPZ-105 |
|---|---|---|---|---|---|---|
| Package | 64-LFCSP-VQ (9x9) | 64-LFCSP-VQ (9x9) - same | 64-LFCSP-VQ (9x9) - same | 64-LFCSP-VQ (9x9) - same | 64-LFCSP-VQ (9x9) - same | 64-LFCSP-VQ (9x9) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 14 bit | 16 bit |
| Sampling Rate (max) | 125 MSPS | 125 MSPS | 105 MSPS | 80 MSPS | 125 MSPS | 105 MSPS |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| SNR @ 70 MHz input | 78.2 dBFS | 78.2 dBFS | 78.2 dBFS | 78.2 dBFS | 75 dBFS | 78.2 dBFS |
| SFDR @ 70 MHz input | 88 dBc | 88 dBc | 88 dBc | 88 dBc | 85 dBc | 88 dBc |
| Power Dissipation | 750 mW | 750 mW | 650 mW | 600 mW | 500 mW | 650 mW |
| Silicon Revision | X (latest) | B (prior) | X | X | X (14-bit variant) | B |
Principais diferenciais
- Latest silicon revision with optimized dynamic performance (vs AD9268BCPZ-125)
- Higher sample rate than lower-cost speed grades (vs AD9268XCPZ-80)
- Higher resolution than the pin-compatible AD9258 (vs AD9258XCPZ-125)
- Dual-channel integration reduces board area (vs Two discrete single-channel 16-bit ADCs)
Notas de projeto
Provide a continuous low-impedance ground plane on the layer directly beneath the AD9268XCPZ-125. Route each AVDD1.8 supply pin through its own 0.1 microfarad ceramic decoupling capacitor placed within 2 mm of the pin, with a 10 microfarad bulk capacitor at the supply entry point. Keep digital output traces (DCO, FCO, DxA/B) away from analog inputs and the sampling clock traces to prevent digital noise coupling into the analog front end.
The exposed thermal pad (EPAD) on pin 64 must be soldered to a filled, grounded copper pad on the PCB. Use at least 8 thermal vias arranged on a 1 mm pitch beneath the EPAD to conduct heat into inner ground planes. Per the AD9268 datasheet, this is required for both electrical reference and thermal dissipation - omitting the EPAD solder connection can degrade SNR by 1 to 2 dB and reduce the junction-to-ambient thermal margin.
Drive the differential sampling clock CLK+/CLK- from a low-jitter source such as the AD9516 or AD9517 clock generator. The datasheet specifies the clock input requires a differential amplitude of approximately 1.5 V peak-to-peak centered on a common-mode voltage supplied by the ADC. Maintain 100 ohm differential impedance on the clock trace pair, and route the pair symmetrically with length matching to within 0.5 mm to preserve 50% duty cycle at the ADC clock input.
Estimated: total power at 125 MSPS is 750 mW from the 1.8 V analog rail plus the digital supply current. A linear regulator with at least 20% headroom over the 750 mW figure is recommended to avoid dropout during transients. If switching regulators are used in the system, place them on a separate PCB region to prevent switching noise from coupling into the analog front end.
Informações de conformidade
RoHS and REACH compliance confirmed by Analog Devices product page. Not AEC-Q100 qualified - this part targets communications, instrumentation, and medical imaging rather than automotive. Refer to AD9268 datasheet for full compliance details.
