ADC1410S105HN/C1:5 - 14-Bit 105MSPS Pipelined ADC | NXP
N.º da peça: ADC1410S105HN/C1:5 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $28.5 | $28,50 |
| 10 | $25.1 | $251,00 |
| 100 | $21.75 | $2.175,00 |
| 500 | $18.4 | $9.200,00 |
| 1.000 | $15.95 | $15.950,00 |
ADC1410S105HN/C1:5 Visão geral
What is a pipelined ADC? A pipelined Analog-to-Digital Converter is a multi-stage converter architecture that uses cascaded low-resolution sub-ADCs to digitize analog signals at high sample rates (tens to hundreds of Msps) while maintaining low latency per conversion cycle. Pipelined ADCs sit in the broader hierarchy of Nyquist-rate ADCs (SAR, pipeline, flash), distinguishing them from oversampling delta-sigma converters; in a signal chain they follow the analog front end (AFE) and feed FPGAs, DSPs, or processors that perform demodulation, FFT, or digital filtering.
Key features of the ADC1410S105HN/C1:5 include 14-bit resolution, 105 Msps maximum sampling rate, selectable CMOS or LVDS DDR digital outputs, serial SPI control interface, integrated input buffering, and 40-pin HVQFN package with thermally efficient exposed pad. The pipelined architecture provides consistent SNR/SFDR performance across the supported 65/80/105/125 Msps family sample rates.
Typical applications for this ADC include communications infrastructure (base stations, IF sampling), industrial imaging (medical ultrasound, machine vision), test and measurement (oscilloscopes, spectrum analyzers), high-speed data acquisition systems, and radar/LIDAR front-ends. The industrial temperature range suits outdoor or harsh-environment deployments.
When designing with the ADC1410S105HN/C1:5, decouple the AVDD pins with 10µF tantalum plus 0.1µF ceramic capacitors placed as close to the pins as possible, and tie the exposed pad to a clean analog ground plane to achieve datasheet thermal resistance. For best SFDR, drive the input in differential mode and use a bandwidth-matched transformer or differential amplifier such as the ADA4937.
This page synthesizes distributor pricing, drop-in alternatives (including 80 Msps, 125 Msps same-family variants and qualified cross-brand pin-compatible parts), and practical design notes not found in the manufacturer datasheet alone.
Alternativas drop-in para ADC1410S105HN/C1:5 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ADC1410S105HN/C1:5 (mesmo formato e footprint) — diferindo em Operating Temperature, Package, Resolution, RoHS Status, Input Type.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ADC1410S125HN/C1:5
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADC1410S080HN/C1:5
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADC1410S065HN/C1:5
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADC1010S105HN/C1:5
✅ Drop-In✓ Em estoque
$9.62 / unidade
Ver ficha técnica →ADC1010S080HN/C1:5
✅ Drop-In✓ Em estoque
$7.32 / unidade
Ver ficha técnica →ADC12C105CISQ
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$9.05 / unidade
Ver ficha técnica →ADC1410S105HN/C1:5 Classificações máximas e características elétricas
| Resolução | 14 bit |
| Number of Channels | 1 |
| Sampling Rate (Max) | 105 Msps |
| Family Sample Rates | 65 / 80 / 105 / 125 Msps (family supports 125 Msps) |
| Architecture | Pipelined |
| Input Type | Differential, Single-Ended |
| Data Interface | Serial, SPI configuration; CMOS or LVDS DDR data outputs |
| Encapsulamento | 40-HVQFN (6x6 mm) with exposed pad |
| Pins | 40 |
| Package Suffix | HN (HVQFN-40, SOT618-6) |
| Temperatura de operação | -40°C to +85°C (industrial) |
| Tipo de montagem | Surface Mount |
| Packaging | Tape & Reel (TR) |
| Status RoHS | Compliant (per NXP datasheet markings) |
| Lead-Free | Yes |
Configuração de pinos do ADC1410S105HN/C1:5
| Pino 1 | VREF — Voltage reference input/output |
| Pino 2 | AVDD — Analog supply |
| Pino 3 | AGND — Analog ground |
| Pino 4 | INP — Differential analog input positive |
| Pino 5 | INN — Differential analog input negative |
| Pino 6 | AGND — Analog ground |
| Pino 7 | CMOUT — Common-mode voltage output for input driver |
| Pino 8 | AGND — Analog ground |
| Pino 9 | AVDD — Analog supply |
| Pino 10 | CLK+ — Differential sampling clock positive |
| Pino 11 | CLK- — Differential sampling clock negative |
| Pino 12 | AVDD — Analog supply |
| Pino 13 | OE/PD — Output enable / power-down control |
| Pino 14 | CSN — SPI chip select (active low) |
| Pino 15 | SCLK — SPI serial clock |
| Pino 16 | SDIO — SPI serial data input/output |
| Pino 17 | SDO — SPI serial data output |
| Pino 18 | DGND — Digital ground |
| Pino 19 | DRVDD — Digital output driver supply |
| Pino 20 | D0 — Data output bit 0 (LSB) |
| Pino 21 | D1 — Data output bit 1 |
| Pino 22 | D2 — Data output bit 2 |
| Pino 23 | D3 — Data output bit 3 |
| Pino 24 | D4 — Data output bit 4 |
| Pino 25 | D5 — Data output bit 5 |
| Pino 26 | D6 — Data output bit 6 |
| Pino 27 | D7 — Data output bit 7 |
| Pino 28 | D8 — Data output bit 8 |
| Pino 29 | D9 — Data output bit 9 |
| Pino 30 | D10 — Data output bit 10 |
| Pino 31 | D11 — Data output bit 11 |
| Pino 32 | D12 — Data output bit 12 |
| Pino 33 | D13 — Data output bit 13 (MSB) |
| Pino 34 | DGND — Digital ground |
| Pino 35 | DRVDD — Digital output driver supply |
| Pino 36 | LVDS/CMOS — Output mode select |
| Pino 37 | TEST1 — Factory test pin, leave floating |
| Pino 38 | TEST2 — Factory test pin, leave floating |
| Pino 39 | DGND — Digital ground |
| Pino 40 | DGND — Digital ground |
Aplicações típicas
ADC1410S105HN/C1:5 é adequado para 6 aplicaçãos: Communications - IF Sampling in Software-Defined Radio, Industrial Imaging - Ultrasound Front-End Receiver, Test and Measurement - Oscilloscope and Spectrum Analyzer Channel, Radar / LIDAR - Wideband Digitizer Front-End, Industrial Data Acquisition - Multi-Channel Vibration Monitoring, Aerospace / Defense - Wideband Electronic-Warfare Receiver.
Communications - IF Sampling in Software-Defined Radio
The ADC1410S105HN/C1:5 is well matched to IF-sampling SDR receivers. Its 105 Msps sample rate comfortably digitizes 70 MHz IF signals from a SAW filter, and the 14-bit resolution gives >75 dB SNR per the NXP datasheet, sufficient to discriminate weak spectral channels. The selectable LVDS DDR output steers data straight into FPGA transceivers, eliminating glue logic and reducing board area. A differential IF driver like the ADA4937 followed by the ADC and a Xilinx Kintex-class FPGA yields a complete multi-channel SDR. Industrial -40°C to +85°C operation suits outdoor base-station deployments and tactical radio platforms.
Recomendado
Industrial Imaging - Ultrasound Front-End Receiver
Medical and industrial ultrasound arrays benefit from the ADC1410S105HN/C1:5's combination of 14-bit resolution and 105 Msps sampling. The pipelined architecture provides low-latency conversion suited to beam-formers operating at 40 MHz carrier, and the exposed-pad HVQFN-40 package keeps channel density high on the receive PCB. Differential inputs reject common-mode noise from piezoelectric transducers, while the SPI interface lets the front-end FPGA tune gain and offset per channel. The industrial -40°C to +85°C grade supports clinical-cart and field-service ultrasound systems without additional thermal management.
Recomendado
Test and Measurement - Oscilloscope and Spectrum Analyzer Channel
Test instruments leverage the ADC1410S105HN/C1:5's 14-bit dynamic range and 105 Msps sustained throughput to digitize broadband analog signals up to the Nyquist band. The LVDS DDR output port streams samples directly into FPGA-based FFT engines at hundreds of MSPS without bus bottlenecks. Operating from -40°C to +85°C allows the part to be used in portable bench-top instruments and on production-line burn-in racks. Combined with a low-jitter clock such as the AD9516 family, the ADC reaches its datasheet SFDR and supplies a clean measurement path for spectrum-analyzer blocks.
Recomendado
Radar / LIDAR - Wideband Digitizer Front-End
Automotive and industrial radar systems require wideband, low-latency analog-to-digital conversion immediately after the IF stage. The ADC1410S105HN/C1:5 offers 105 Msps of sampling with 14-bit resolution, capturing 40-60 MHz IF outputs from a mixer while preserving phase linearity for FMCW chirp processing. The 40-HVQFN package with exposed pad offers good thermal performance for sustained operation, and the LVDS DDR digital interface mates cleanly with Xilinx or Lattice FPGAs implementing corner-point FFT and target detection. Industrial temperature range is adequate for non-automotive radar and machine-vision LIDAR deployments.
Recomendado
Industrial Data Acquisition - Multi-Channel Vibration Monitoring
Industrial condition-monitoring systems digitize accelerometer outputs at 50 ksps to 100 Msps; for high-bandwidth vibration analysis on rotating machinery the ADC1410S105HN/C1:5 provides 105 Msps oversampling to relax anti-alias filter design. The 14-bit dynamic range lets the system resolve both low-amplitude bearing faults and large rotor unbalances within a single gain stage. Differential inputs reject common-mode ground-loop noise common in factory-floor installations, and the SPI configuration interface simplifies per-channel calibration in dense multi-board installations. Industrial temperature range supports gearbox, pump, and motor monitoring in unattended cabinets.
Recomendado
Aerospace / Defense - Wideband Electronic-Warfare Receiver
Electronic-warfare and SIGINT subsystems need wideband digitization of intermediate-frequency outputs. The ADC1410S105HN/C1:5 supports 105 Msps sampling of 50 MHz IF signals with 14-bit dynamic range, allowing capture and digital-channelization of multiple simultaneous emitters. Its LVDS DDR output permits routing data directly to a Xilinx Kintex FPGA implementing a channelizer/DDC, and the industrial temperature grade tolerates mission-computing bay environments where -40°C to +85°C is required. Pin compatibility with the family ADC1410S125HN/C1:5 also makes it easy to scale to higher instantaneous-bandwidth EW designs without redesigning the PCB.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ADC1410S105HN/C1:5 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ADC1410S125HN/C1:5 | ADC1410S080HN/C1:5 | ADC1410S065HN/C1:5 | ADC1010S105HN/C1:5 | ADC12C105CISQ |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors - same | NXP Semiconductors - same | NXP Semiconductors - same | NXP Semiconductors - same | NXP Semiconductors - same |
| Package | 40-HVQFN (6x6) | 40-HVQFN (6x6) - same | 40-HVQFN (6x6) - same | 40-HVQFN (6x6) - same | 40-HVQFN (6x6) - same | 40-HVQFN (6x6) - same |
| Resolution | 14 bit | 14 bit - same | 14 bit - same | 14 bit - same | 10 bit | 12 bit |
| Sample Rate | 105 Msps | 125 Msps (+19%) | 80 Msps (-24%) | 65 Msps (-38%) | 105 Msps - same | 105 Msps - same |
| Architecture | Pipelined | Pipelined - same | Pipelined - same | Pipelined - same | Pipelined - same | Pipelined - same |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Output Interface | CMOS or LVDS DDR | CMOS or LVDS DDR - same | CMOS or LVDS DDR - same | CMOS or LVDS DDR - same | CMOS or LVDS DDR - same | CMOS only |
| Configuration Interface | SPI (serial) | SPI (serial) - same | SPI (serial) - same | SPI (serial) - same | SPI (serial) - same | SPI (serial) - same |
| Operating Temperature | -40°C to +85°C | -40°C to +85°C - same | -40°C to +85°C - same | -40°C to +85°C - same | -40°C to +85°C - same | -40°C to +85°C - same |
| Approx 1k Price (USD) | 15.95 | ~22.00 (higher speed, higher cost) | ~14.50 | ~13.20 | ~9.80 (10-bit, lower cost) | ~12.40 (12-bit) |
Principais diferenciais
- 14-bit resolution at 105 Msps in a single 40-HVQFN footprint (vs ADC1010S105HN/C1:5)
- Mid-tier sample rate with pin-compatible upgrade to 125 Msps (vs ADC1410S065HN/C1:5)
- Selectable CMOS or LVDS DDR outputs (vs ADC12C105CISQ)
- NXP industrial-grade reliability (vs Generic 14-bit 105 Msps third-party ADCs)
Notas de projeto
Per NXP datasheet PCB layout recommendations, place 10µF tantalum plus 0.1µF ceramic decoupling capacitors as close as possible to each AVDD and DRVDD pin. Use a single solid analog ground plane under the HVQFN exposed pad and stitch the digital ground returns around the periphery to prevent digital switching noise from coupling into the analog front end.
Drive the ADC1410S105HN/C1:5 in differential mode for best SFDR; the NXP datasheet shows single-ended operation typically loses 10-15 dB of SFDR above 70 MHz. Use a bandwidth-matched transformer or differential amplifier such as the ADA4937 between the IF stage and the ADC INP/INN inputs, and route the two traces as a length-matched 100 ohm differential pair.
Provide a low-jitter, low-phase-noise sampling clock such as the AD9516 to the CLK+/CLK- inputs; per the NXP datasheet aperture jitter of the ADC can be degraded by 10:1 by clock jitter. Route the clock traces as 100 ohm differential, length-matched to within 100 mil of the analog input pair, and terminate close to the ADC pins.
Solder the HVQFN exposed pad to a continuous ground plane with at least 4 thermal vias (0.3 mm drill, 1.0 mm pitch) directly under the pad to achieve the datasheet theta-JA. Without the exposed-pad solder connection the junction temperature rises 30-40°C above the calculated value, potentially triggering thermal shutdown during sustained 105 Msps operation.
Do not float the LVDS/CMOS mode-select pin; tie it to DRVDD for LVDS DDR or to DGND for CMOS outputs per the NXP datasheet configuration table. Floating the pin can place the output drivers in an undefined state and draw excessive bias current from DRVDD. Also connect unused SPI SDO/SDIO per the datasheet bypass procedure during factory test.
Informações de conformidade
NXP datasheet marks the part RoHS compliant and lead-free. Industrial grade -40°C to +85°C; not AEC-Q100 qualified (use Q-grade NXP ADCs for automotive under-hood applications).
