ADS5546IRGZR - 14-Bit 190 MSPS ADC, DDR LVDS/CMOS | Texas Instruments
N.º da peça: ADS5546IRGZR ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $38.95 | $38,95 |
| 10 | $35.2 | $352,00 |
| 100 | $31.5 | $3.150,00 |
| 500 | $27.8 | $13.900,00 |
| 1.000 | $24.95 | $24.950,00 |
ADS5546IRGZR Visão geral
An ADC (analog-to-digital converter) is a data-conversion IC that translates a continuous-time, continuous-amplitude analog input into a discrete digital code word at a specified sample rate. The ADS5546 belongs to TI's high-speed pipeline ADC family, sitting in the wider hierarchy of Nyquist-rate data converters and in the broader category of mixed-signal/data-converter semiconductors that include SAR, sigma-delta, and flash converters. Pipeline ADCs like the ADS5546 strike a balance between the high sampling rates needed for IF sampling in communications and the moderate-to-high resolution required by imaging and instrumentation systems.
Key features per the TI datasheet include a 190 MSPS maximum sample rate, 14-bit guaranteed no-missing-codes resolution, 73.2 dBFS SNR at 70-MHz IF input, 87 dBc SFDR at 70-MHz IF input (0 dB gain), and both DDR LVDS and parallel CMOS digital interfaces. The internal sample-and-hold architecture delivers excellent AC performance while accepting either an internal or external reference, eliminating the need for external reference decoupling.
Internally the converter uses a multi-stage pipeline core with proprietary calibration logic to maintain low distortion across the input bandwidth. The selectable output format (DDR LVDS or parallel CMOS) lets designers choose between high-speed serial-style LVDS links (for FPGA/ASIC multi-channel boards) and lower-rate CMOS buses (for standard FPGAs), simplifying integration into either architecture.
Typical applications include communications IF sampling in base stations, 3G/4G wireless receivers, medical imaging front ends such as ultrasound beamformers, defense radar signal processing, and high-end instrumentation such as digital oscilloscopes and spectrum analyzers. The wide input bandwidth and high SNR also suit it to wideband satellite and test-and-measurement receivers.
Designers should plan PCB layout with separate analog and digital ground planes joined at a single point near the IC, place bypass capacitors (typically 0.1 microfarad ceramic plus bulk tantalum) close to each supply pin, and route the DDR LVDS pairs as 100-ohm differential transmission lines to the receiving FPGA. Thermally, the part dissipates roughly 1.1 W at 190 MSPS with full-scale input - verify the 7x7 mm VQFN thermal pad layout provides sufficient copper to keep the junction within the industrial temperature range.
This page synthesizes distributor pricing and availability, drop-in alternatives from the ADS55xx family and competitors, and practical PCB/high-speed design notes that are not included in the TI datasheet application section.
Alternativas drop-in para ADS5546IRGZR — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ADS5546IRGZR (mesmo formato e footprint) — diferindo em Package, Input Type, Operating Temperature Range, Resolution, SFDR.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ADS5546IRGZ25
✅ Drop-In✓ Em estoque
$24.95 / unidade
Ver ficha técnica →ADS5547IRGZR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS5545IRGZR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS6242IRGZR
✅ Drop-In✓ Em estoque
$18.25 / unidade
Ver ficha técnica →ADS5559IRGZR
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
AD9254BCPZ-150
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS5546IRGZR Classificações máximas e características elétricas
| Resolução | 14 bits |
| Architecture | Pipelined |
| Number of Inputs | 1 |
| Maximum Sample Rate | 190 MSPS |
| Input Type | Single-ended analog (differential internal) |
| Tipo de saída | DDR LVDS or Parallel CMOS (user-selectable) |
| Analog Supply Voltage | 3.3 V (typical) |
| Digital Supply Voltage | 3.3 V (typical) |
| Total Power Dissipation | 1.1 W (typical at 190 MSPS) |
| SNR | 73.2 dBFS at 70-MHz IF input |
| SFDR | 87 dBc at 70-MHz IF input, 0 dB gain |
| Internal Reference | Yes (external reference supported) |
| Integral Nonlinearity (typ) | 0.0305 % per FindIC listing |
| Faixa de temperatura de operação | -40C to +85C (industrial) |
| Encapsulamento | 48-VQFN (7x7 mm, RGZ) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Number of Terminals | 48 |
Configuração de pinos do ADS5546IRGZR
| Pino 1 | AVDD — Analog 3.3 V supply |
| Pino 2 | INP — Positive analog input |
| Pino 3 | INN — Negative analog input |
| Pino 4 | AGND — Analog ground |
| Pino 5 | REFT — Internal reference top decoupling |
| Pino 6 | REFB — Internal reference bottom decoupling |
| Pino 7 | REFEN — Reference enable / select |
| Pino 8 | VCM — Common-mode voltage output |
| Pino 9 | AVDD — Analog 3.3 V supply |
| Pino 10 | AGND — Analog ground |
| Pino 11 | CLKp — Differential clock input positive |
| Pino 12 | CLKn — Differential clock input negative |
| Pino 13 | AVDD — Analog 3.3 V supply |
| Pino 14 | AGND — Analog ground |
| Pino 15 | DVDD — Digital 3.3 V supply |
| Pino 16 | DGND — Digital ground |
| Pino 17 | RESET — Global reset, active logic level per datasheet |
| Pino 18 | PDN — Power-down input |
| Pino 19 | OUTMODE — Selects DDR LVDS or parallel CMOS output |
| Pino 20 | DGND — Digital ground |
| Pino 21 | D0P — LVDS data output 0 positive (DDR mode) |
| Pino 22 | D0N — LVDS data output 0 negative |
| Pino 23 | D1P — LVDS data output 1 positive |
| Pino 24 | D1N — LVDS data output 1 negative |
| Pino 25 | DGND — Digital ground |
| Pino 26 | D2P — LVDS data output 2 positive |
| Pino 27 | D2N — LVDS data output 2 negative |
| Pino 28 | D3P — LVDS data output 3 positive |
| Pino 29 | D3N — LVDS data output 3 negative |
| Pino 30 | D4P — LVDS data output 4 positive |
| Pino 31 | D4N — LVDS data output 4 negative |
| Pino 32 | D5P — LVDS data output 5 positive |
| Pino 33 | D5N — LVDS data output 5 negative |
| Pino 34 | D6P — LVDS data output 6 positive |
| Pino 35 | D6N — LVDS data output 6 negative |
| Pino 36 | D7P — LVDS data output 7 positive |
| Pino 37 | D7N — LVDS data output 7 negative |
| Pino 38 | DCLKP — DDR LVDS data clock output positive |
| Pino 39 | DCLKN — DDR LVDS data clock output negative |
| Pino 40 | DVDD — Digital 3.3 V supply |
| Pino 41 | DGND — Digital ground |
| Pino 42 | D8 — CMOS data output 8 (parallel CMOS mode) |
| Pino 43 | D9 — CMOS data output 9 |
| Pino 44 | D10 — CMOS data output 10 |
| Pino 45 | D11 — CMOS data output 11 |
| Pino 46 | D12 — CMOS data output 12 |
| Pino 47 | D13 — CMOS data output 13 (MSB) |
| Pino 48 | EP — Exposed thermal pad - tie to AGND |
Aplicações típicas
ADS5546IRGZR é adequado para 6 aplicaçãos: Wireless Base Station IF Sampling, Medical Ultrasound Beamforming, Defense & Electronic Warfare Receivers, Test & Measurement Instrumentation, Satellite Communication Receivers, Software-Defined Radio (SDR) Platforms.
Wireless Base Station IF Sampling
The ADS5546IRGZR's 14-bit, 190 MSPS sampling rate supports direct IF sampling of intermediate frequencies up to ~90 MHz in the second Nyquist zone, eliminating mixers and SAW filters in macro-cell base stations. With 73.2 dBFS SNR and 87 dBc SFDR at 70-MHz IF input, the part preserves dynamic range needed for UMTS, LTE, and 5G NR receiver chains. The selectable DDR LVDS output streams samples cleanly into a DSP or FPGA implementing digital downconversion, while the parallel CMOS mode serves ASIC-based receiver SoCs.
Recomendado
Medical Ultrasound Beamforming
Ultrasound front ends require high-resolution, high-throughput ADCs to digitize beam-formed RF returns from piezoelectric transducers. The ADS5546IRGZR's 14-bit resolution combined with 190 MSPS sample rate captures the full dynamic range of tissue echoes while preserving the harmonic bandwidth needed for harmonic-imaging modes. The part's pipeline architecture delivers low-latency data paths, and the DDR LVDS interface streams sample bursts directly into FPGA-based beamformers used in portable cart-based and handheld ultrasound systems.
Recomendado
Defense & Electronic Warfare Receivers
Electronic-warfare, signals-intelligence, and radar-warning receiver systems require wideband digitization of intermediate frequencies for immediate real-time threat classification. The ADS5546IRGZR's 190 MSPS throughput and 87 dBc SFDR capture small signals masked by adjacent jammers, while the 14-bit dynamic range preserves sub-1 dB amplitude steps needed for direction-finding. Internal precision reference stabilization limits drift over temperature extremes encountered in military fielded equipment.
Recomendado
Test & Measurement Instrumentation
Digital oscilloscopes, spectrum analyzers, and wideband signal recorders depend on high-ENOB pipeline ADCs to digitize waveforms for FFT and time-domain analysis. The ADS5546IRGZR's 73.2 dBFS SNR translates to ~11.8 effective bits, well suited to benchtop oscilloscope input channels sampling at up to 190 MSPS. Industrial temperature grade (-40C to +85C) supports laboratory benchtop products and portable field recorders that must operate in uncontrolled thermal environments.
Recomendado
Satellite Communication Receivers
L-band and S-band satellite-comm receivers downconvert microwave carriers to an IF where wideband ADC sampling becomes feasible. The ADS5546IRGZR's 190 MSPS rate accepts IFs in the 100-150 MHz range with margin, while 73.2 dBFS SNR supports the small-signal carrier-to-noise budgets of digital satellite TV and broadband VSAT ground terminals. The 48-VQFN package and 1.1 W power dissipation suit outdoor-unit thermal constraints at the antenna hub.
Recomendado
Software-Defined Radio (SDR) Platforms
Wideband software-defined radios tune and demodulate multiple waveforms in software, requiring ADCs that digitize large instantaneous bandwidths at high dynamic range. The ADS5546IRGZR's selectable DDR LVDS or CMOS digital interfaces let designers match the FPGA's preferred IO standard, while the 190 MSPS sample rate covers up to ~95 MHz of instantaneous bandwidth. Engineers can build single-board SDR platforms capable of demodulating everything from FM broadcast to cellular downlink by tuning the analog front end and feeding the digital stream into an FPGA or DSP.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ADS5546IRGZR — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ADS5546IRGZ25 | ADS5547IRGZR | ADS5545IRGZR | ADS5559IRGZR | AD9254BCPZ-150 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Analog Devices |
| Package | 48-VQFN (7x7 mm, RGZ) | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-LFCSP (7x7) - compatible footprint |
| Resolution | 14 bits | 14 bits | 14 bits | 14 bits | 14 bits | 14 bits |
| Sample Rate | 190 MSPS | 190 MSPS | 210 MSPS | 125 MSPS | 250 MSPS (2 channels) | 150 MSPS |
| Channels | 1 | 1 | 1 | 1 | 2 | 1 |
| Output Type | DDR LVDS / CMOS selectable | DDR LVDS / CMOS selectable | DDR LVDS / CMOS selectable | DDR LVDS / CMOS selectable | DDR LVDS / CMOS selectable | LVDS only |
| Total Power Dissipation | 1.1 W | 1.1 W | 1.2 W (typ) | ~0.8 W (typ) | ~1.5 W (typ) | ~0.8 W (typ) |
| Approx Unit Price (1k qty) | $24.95 | $25-28 | $32-36 | $18-22 | $45-55 | $40-48 |
Principais diferenciais
- User-selectable DDR LVDS or parallel CMOS digital output (vs AD9254BCPZ-150)
- Higher maximum sample rate at same 14-bit resolution (vs AD9254BCPZ-150)
- Single-channel high-throughput 14-bit pipeline in 48-VQFN (vs ADS5559IRGZR)
- Direct drop-in compatibility with the ADS5547 family (vs ADS5547IRGZR)
Notas de projeto
Use a 6-layer stack-up with separate analog and digital ground planes joined at a single-point star ground beneath the IC. Place 0.1 microfarad X7R ceramic bypass capacitors within 3 mm of every AVDD, DVDD, and REFT/REFB pin, plus a 10 microfarad tantalum bulk capacitor near the AVDD pad. The exposed thermal pad (pin 48) must be soldered to a copper island tied to analog ground; thermal vias (12 to 16 of 0.3 mm diameter) beneath the pad spread heat into an inner ground plane. Estimated: at 1.1 W dissipation the junction rise above ambient with the recommended layout is approximately 25-30 C at 25C ambient.
Route the analog INP/INN inputs as a tightly-coupled 100-ohm differential pair with matched lengths to within 0.5 mm to preserve the 73.2 dBFS SNR. The CLKp/CLKn clock inputs must be similarly routed; clock jitter directly multiplies into ADC aperture jitter - keep clock traces short and away from digital switching lines. The DDR LVDS data outputs (D0P/N through D7P/N and DCLKP/N) should be controlled-impedance 100-ohm differential routes terminated at the FPGA with 100-ohm parallel resistors to keep rising edges clean at the higher sample rate.
Do not operate the ADS5546 without proper REFEN pin configuration - the internal reference requires the correct logic state at startup and a 10 microfarad low-ESR capacitor on REFT/REFB for stability. Common design errors include leaving AVDD floating between pins, failing to provide low-impedance clock (CMOS or PECL) to the CLK inputs, and applying common-mode voltages outside the datasheet range. Also: do not deselect PDN until analog supplies have stabilized; power-up sequencing from 3.3 V AVDD first, then DVDD is recommended.
Informações de conformidade
RoHS/REACH compliance per TI semiconductor product family. Industrial temperature grade (-40C to +85C) is offered; AEC-Q100 automotive qualified variants exist as ADS5546IRGZR-Q1 family part (verify exact suffix with distributor).
