ADS5562IRGZ25 - 16-bit 80MSPS ADC LVDS/CMOS | Texas Instruments
N.º da peça: ADS5562IRGZ25 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $34.65 | $346,50 |
| 100 | $30.8 | $3.080,00 |
| 500 | $27.95 | $13.975,00 |
| 1.000 | $25.12 | $25.120,00 |
ADS5562IRGZ25 Visão geral
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples continuous-time analog voltages and converts them into discrete digital codes for processing by DSPs, FPGAs, or microcontrollers. High-speed ADCs sit at the data-acquisition front end of communications receivers, instrumentation digitizers, and medical imaging systems, translating real-world analog waveforms into the digital domain at sample rates that must preserve the spectral content of the input signal. The ADS5562 family belongs to the pipelined-ADC architecture class, which delivers multi-Msample/s rates at moderate power and resolution; within the wider hierarchy it is a data-converter > ADC > high-speed ADC > semiconductor IC.
Key device features include 16-bit resolution with no missing codes, programmable fine gain in 1 dB steps up to 6 dB, an internal low-frequency noise suppression mode, and flexible DDR LVDS or parallel CMOS output interfaces that ease interfacing with ASICs and FPGAs. The pipelined architecture multiplies per-stage resolution by interleaving sample-and-hold stages, allowing high effective sampling rates while limiting per-stage complexity.
Typical applications include multi-carrier GSM/EDGE/LTE base-station receivers, radar signal processing chains, cable-infrastructure head-end equipment, medical ultrasound beamformers, and high-end laboratory test instrumentation. Designers choose the ADS5562IRGZ25 when the system requires 16-bit linearity combined with 80 MSPS throughput in a compact, thermally-efficient package.
When laying out the PCB, route the differential clock with 100 ohm controlled-impedance traces, keep analog inputs short and symmetric to preserve SFDR, and provide ample ground planes around the exposed thermal pad. The output mode (LVDS vs CMOS) and word/data formatting must be selected before PLL locking, as changes after lock may corrupt captured samples.
Alternativas drop-in para ADS5562IRGZ25 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ADS5562IRGZ25 (mesmo formato e footprint) — diferindo em Resolution, Programmable Gain, Input Type, Operating Temperature Range, Analog Supply Voltage.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ADS5560IRGZ
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
ADS5562IRGZ25G4
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS5562IRGZR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS5562IRGZT
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS62P48IRGC25
✅ Drop-In✓ Em estoque
$49.2 / unidade
Ver ficha técnica →ADS5546IRGZRG4
✅ Drop-In✓ Em estoque
$21.55 / unidade
Ver ficha técnica →ADS61B29IRGZ25
✅ Drop-In✓ Em estoque
$17.8 / unidade
Ver ficha técnica →ADS5562IRGZ25 Classificações máximas e características elétricas
| Resolução | 16 bits |
| Sample Rate (max) | 80 MSPS |
| Sample Rate (low-power mode) | 40 MSPS |
| Number of Input Channels | 1 |
| Architecture | Pipelined |
| SNR at 3 MHz IF | 84 dBFS |
| SFDR at 3 MHz IF | 85 dBc |
| Output Interface | DDR LVDS / Parallel CMOS (selectable) |
| Input Type | Differential |
| Programmable Gain | 1 dB steps up to 6 dB |
| Low-Frequency Noise Suppression | Yes (DC to ~1 MHz) |
| Encapsulamento | 48-VQFN (RGZ) 7x7 mm with exposed pad |
| Faixa de temperatura de operação | -40 C to +85 C (Industrial) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Lead-Free | Yes |
Configuração de pinos do ADS5562IRGZ25
| Pino 1 | AVDD — Analog supply voltage |
| Pino 2 | AVDD — Analog supply voltage |
| Pino 3 | GND — Analog ground |
| Pino 4 | GND — Analog ground |
| Pino 5 | INP — Differential analog input (positive) |
| Pino 6 | INM — Differential analog input (negative) |
| Pino 7 | VCM — Common-mode voltage output |
| Pino 8 | REF — Internal reference decoupling |
| Pino 9 | REFT — Reference top decoupling |
| Pino 10 | REFB — Reference bottom decoupling |
| Pino 11 | GND — Analog ground |
| Pino 12 | VREF — Voltage reference |
| Pino 13 | RESET — Hardware reset, active low |
| Pino 14 | PD — Power-down control |
| Pino 15 | CLKP — Differential clock input (positive) |
| Pino 16 | CLKM — Differential clock input (negative) |
| Pino 17 | GND — Clock ground |
| Pino 18 | DRVDD — Digital output supply |
| Pino 19 | GND — Digital ground |
| Pino 20 | D0_DOUT0P — LVDS data output 0 positive / CMOS D0 |
| Pino 21 | D0_DOUT0M — LVDS data output 0 negative |
| Pino 22 | D1_DOUT1P — LVDS data output 1 positive / CMOS D1 |
| Pino 23 | D1_DOUT1M — LVDS data output 1 negative |
| Pino 24 | D2_DOUT2P — LVDS data output 2 positive / CMOS D2 |
| Pino 25 | D2_DOUT2M — LVDS data output 2 negative |
| Pino 26 | D3_DOUT3P — LVDS data output 3 positive / CMOS D3 |
| Pino 27 | D3_DOUT3M — LVDS data output 3 negative |
| Pino 28 | D4_DOUT4P — LVDS data output 4 positive / CMOS D4 |
| Pino 29 | D4_DOUT4M — LVDS data output 4 negative |
| Pino 30 | D5_DOUT5P — LVDS data output 5 positive / CMOS D5 |
| Pino 31 | D5_DOUT5M — LVDS data output 5 negative |
| Pino 32 | D6_DOUT6P — LVDS data output 6 positive / CMOS D6 |
| Pino 33 | D6_DOUT6M — LVDS data output 6 negative |
| Pino 34 | D7_DOUT7P — LVDS data output 7 positive / CMOS D7 |
| Pino 35 | D7_DOUT7M — LVDS data output 7 negative |
| Pino 36 | D8_DOUT8 — CMOS D8 / LVDS framing bit |
| Pino 37 | D9_DOUT9 — CMOS D9 / LVDS framing bit |
| Pino 38 | D10_DCLKOUTP — CMOS D10 / LVDS clock output positive |
| Pino 39 | D11_DCLKOUTM — CMOS D11 / LVDS clock output negative |
| Pino 40 | FS — Frame sync output |
| Pino 41 | SEN — Serial interface enable |
| Pino 42 | SCLK — Serial interface clock |
| Pino 43 | SDATA — Serial interface data |
| Pino 44 | MODE — LVDS/CMOS mode select |
| Pino 45 | OF — Out-of-range flag |
| Pino 46 | GAIN0 — Programmable gain control bit 0 |
| Pino 47 | GAIN1 — Programmable gain control bit 1 |
| Pino 48 | GAIN2 — Programmable gain control bit 2 |
Aplicações típicas
ADS5562IRGZ25 é adequado para 6 aplicaçãos: Multi-Carrier GSM/EDGE/LTE Base-Station Receiver, Medical Ultrasound Beamformer Front-End, Radar Signal Processing Digitizer, Cable Infrastructure Head-End Digitizer, High-End Test and Measurement Instrumentation, Software-Defined Radio Receiver.
Multi-Carrier GSM/EDGE/LTE Base-Station Receiver
The ADS5562IRGZ25 fits multi-carrier GSM/EDGE/LTE base-station receiver IF digitizers because its 80 MSPS sampling rate and 84 dBFS SNR with 85 dBc SFDR at 3 MHz IF preserve signal integrity across multiple adjacent carriers. Designers place the ADC after the final mixer and SAW filter, driving its differential analog input from a low-noise differential op-amp like the THS4509. The DDR LVDS output mode streams data into the FPGA channelizer; alternatively, the CMOS mode simplifies test-and-measurement capture. The 40 MSPS low-power mode lets the same hardware trade throughput for power when fewer carriers are active, giving base-station OEMs a single BOM across multiple product variants.
Recomendado
Medical Ultrasound Beamformer Front-End
In medical ultrasound beamformers, the ADS5562IRGZ25 digitizes the post-TGC analog channel at 80 MSPS with 16-bit resolution that captures the wide dynamic range of returned echoes. The exposed thermal pad and 7x7 mm VQFN footprint allow dense placement behind multi-element transducers, while the industrial -40 C to +85 C temperature range meets clinical equipment requirements. The low-frequency noise suppression mode reduces flicker noise from DC to about 1 MHz, improving low-frequency harmonic imaging. DDR LVDS outputs feed the channel FPGA that performs delay-and-sum beamforming, keeping latency low. Beamformer OEMs typically run the ADC at 40 MSPS for portable carts and 80 MSPS for premium cart systems.
Recomendado
Radar Signal Processing Digitizer
Radar signal-processing chains such as pulsed-Doppler weather radar and synthetic-aperture radar IF stages use the ADS5562IRGZ25 for its combination of 80 MSPS sampling and high spurious-free dynamic range. Radar receivers typically down-convert to a 5-30 MHz IF where the ADC's 84 dBFS SNR ensures small target returns are not masked by spectral noise, while SFDR keeps strong returns from generating spurs that mimic real targets. The pipelined architecture provides low aperture jitter, which preserves the sub-microsecond time-of-arrival accuracy that radar processing depends on. The selectable LVDS output mode interfaces directly to Xilinx or Altera FPGAs that implement the matched-filter and FFT stages, simplifying the digital board layout.
Recomendado
Cable Infrastructure Head-End Digitizer
Cable infrastructure head-end equipment uses the ADS5562IRGZ25 to digitize downstream QAM or OFDM channels at the optical-node return path. The 80 MSPS rate captures multiple adjacent cable channels with sufficient oversampling to relax the analog anti-alias filter design. The 16-bit resolution supports 256-QAM and 1024-QAM constellations where the noise floor must remain well below the symbol decision thresholds. Its programmable 1 dB gain step to 6 dB enables channel-by-channel RF power equalization in software, reducing the precision required of upstream analog attenuators. The DDR LVDS interface feeds the demodulator ASIC, while the CMOS mode supports low-cost FPGA-based designs for rural DOCSIS deployments.
Recomendado
High-End Test and Measurement Instrumentation
In high-end test and measurement instruments such as digital oscilloscopes, spectrum analyzers, and arbitrary waveform generator capture paths, the ADS5562IRGZ25 provides the 16-bit resolution and 80 MSPS rate needed to digitize waveforms with high DC and AC accuracy. The pipelined ADC combined with the low-frequency noise suppression mode (DC to ~1 MHz) yields a true 16-bit noise floor that exceeds typical 14-bit oscilloscope ADCs. The CMOS output mode is often preferred in this segment to simplify logic analyzer or FPGA post-processing, while the LVDS mode supports multi-channel interleaved architectures. The exposed thermal pad and standard 48-VQFN footprint allow dense multi-board layouts used in modular instruments.
Recomendado
Software-Defined Radio Receiver
Software-defined radio (SDR) receiver platforms benefit from the ADS5562IRGZ25's 80 MSPS throughput and 84 dBFS SNR which allows a wide IF swath to be captured and tuned digitally. Designers place the ADC at the output of the final mixer and SAW filter, then stream DDR LVDS samples into an FPGA running multi-channel DDC firmware. The high SFDR ensures spur-free operation across the captured spectrum, critical for weak-signal detection in amateur radio, public-safety, and electronic-warfare applications. The exposed thermal pad and industrial temperature range support ruggedized enclosures used in field-deployed SDR platforms, while the 40 MSPS low-power mode enables battery operation with reduced throughput.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ADS5562IRGZ25 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ADS5560IRGZ | ADS5562IRGZ25G4 | ADS5562IRGZR | ADS62P48IRGC25 | ADS5546IRGZRG4 |
|---|---|---|---|---|---|---|
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 16 bits | 16 bits | 16 bits | 16 bits | 14 bits | 14 bits |
| Maximum Sample Rate | 80 MSPS | 40 MSPS | 80 MSPS | 80 MSPS | 200 MSPS | 40 MSPS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Output Interface | DDR LVDS / CMOS | DDR LVDS / CMOS | DDR LVDS / CMOS | DDR LVDS / CMOS | LVDS | DDR LVDS / CMOS |
| Number of Input Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Temperature Range | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Principais diferenciais
- Higher sample rate without changing the PCB layout (vs ADS5560IRGZ)
- Higher resolution for narrowband radar and instrumentation (vs ADS5546IRGZRG4)
- DDR LVDS and parallel CMOS interface for flexible FPGA integration (vs ADS62P48IRGC25)
Notas de projeto
Route the analog input traces (INP, INM) as a matched-length differential pair with 100 ohm differential impedance. Keep these traces symmetric and short (under 1 cm) to preserve the 85 dBc SFDR at 3 MHz IF. Place the VCM bypass capacitor pin-7 directly on the printed circuit board without sharing vias with the AVDD decoupling. Ground the exposed thermal pad with at least nine thermal vias to the inner ground plane to keep junction temperature rise under 15 C in still air.
Estimated: with AVDD approximately 3.3 V, DRVDD approximately 1.8 V, the ADC consumes in the order of 600 mW total at 80 MSPS. Provide separate analog and digital supplies, each decoupled with a 10 uF bulk capacitor plus 100 nF and 10 nF ceramics placed within 2 mm of the supply pins. Series ferrite beads between AVDD and DRVDD prevent digital switching noise from coupling back into the analog supply, which would degrade SNR from 84 dBFS to a lower figure.
Keep the digital output bus (D0-D11, DCLKOUT, FS) routed on the opposite side of the board from the analog input network. Do not cross analog and digital traces to avoid digital switching edges coupling into the input. The output timing is source-synchronous in LVDS mode; therefore the DCLKOUTP/M traces must be length-matched to the data traces within 25 ps (about 3 mm) for the 80 MSPS DDR interface to meet setup/hold at the FPGA capture register.
Do not select LVDS mode and then apply a single-ended CMOS clock to CLKP/CLKM - the ADC will not handshake correctly and the outputs may exhibit glitches. Always drive the clock as a true 100 ohm differential LVPECL or LVDS signal, terminated at the device pins. Before power-up, hold RESET low for at least 100 ns with PD high to ensure a clean initialization. Switching between LVDS and CMOS output modes after startup can corrupt the next data frame; toggle output mode in reset state only.
Although the ADS5562 achieves 84 dBFS SNR and 85 dBc SFDR, system-level noise can quickly degrade these numbers if the reference decoupling is not optimized. Use a low-ESR 1 uF X7R capacitor on REFT and REFB, located within 1 mm of the respective pins, to suppress reference ripple that would otherwise couple into the input sample-and-hold. For multi-IF applications, enable the low-frequency noise suppression mode (register bit) to extend useful SNR down to DC and improve detection of low-frequency targets.
Informações de conformidade
RoHS-compliant per TI product page. The -Q1 suffix variant provides AEC-Q100 qualification when required; the standard ADS5562IRGZ25 is not automotive-qualified.
