ADS6224IRGZ25 - Dual 12-Bit 105MSPS ADC LVDS | Texas Instruments
N.º da peça: ADS6224IRGZ25 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $49.5 | $49,50 |
| 10 | $44.55 | $445,50 |
| 100 | $39.6 | $3.960,00 |
| 500 | $35.2 | $17.600,00 |
| 1.000 | $31.25 | $31.250,00 |
ADS6224IRGZ25 Visão geral
A pipelined ADC is a high-speed data-converter architecture that resolves each input sample through a chain of low-resolution stages with digital error correction, delivering high sample rates (tens to hundreds of MSPS) at moderate resolution (8-14 bits). Pipelined ADCs sit higher than successive-approximation (SAR) ADCs in the speed/resolution trade-off but lower than flash ADCs in raw analog bandwidth; they are members of the broader data-converter IC family, which also includes delta-sigma, SAR, and flash topologies. The ADS6224 belongs to TI's high-speed converter portfolio targeting communications, instrumentation, and defense imaging subsystems.
Key features include a maximum sample rate of 125 MSPS (the 105-MSPS grade shipped as IRGZ25 is pin-compatible with the 65/80/105/125 MSPS variants), simultaneous sample-and-hold for both channels, a 3.5 dB coarse gain option plus a 6 dB programmable fine gain, serialized LVDS output for low-EMI high-speed data transfer, and a 1.8 V analog / 3.3 V LVDS supply split. Total power dissipation is approximately 320 mW per channel at 105 MSPS, and the LVDS interface reduces board-routing complexity versus parallel CMOS outputs at >100 MSPS.
The ADS6224 uses a multi-stage pipeline with an internal sample-and-hold and supports both single-wire and dual-wire LVDS serialization to flex with board density and FPGA capture budgets. Its LVDS topology generates far less switching noise than parallel CMOS outputs, easing EMI compliance in dense multi-channel systems such as 4G base-station receivers and phased-array radar digitizers.
Typical applications include communications base-station receivers (multi-carrier GSM, LTE, WCDMA), multi-channel wireless infrastructure, medical imaging front-ends (ultrasound beamformers), defense and instrumentation (synthetic aperture radar, oscilloscope data acquisition), and dual-channel IF-sampling designs where both I and Q paths must be digitized concurrently with matched gain.
When designing with this device, decouple AVDD (1.8 V) and LVDDR (3.3 V) supplies independently with 1 µF + 100 nF ceramic capacitors placed within 5 mm of the supply pins, and provide a solid low-impedance ground plane under the exposed thermal pad. Route the LVDS output pairs with 100 Ω differential impedance and length-match within 150 ps to minimize inter-symbol jitter at the FPGA receiver.
This page synthesizes distributor pricing, drop-in same-package alternatives (ADS6242IRGZR, ADS6243IRGZR, ADS6244IRGZRG4 from the same TI family), and practical design notes not found on the bare manufacturer datasheet.
Alternativas drop-in para ADS6224IRGZ25 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ADS6224IRGZ25 (mesmo formato e footprint) — diferindo em Operating Temperature Range, Package, Resolution, Input Type, Number of Channels.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ADS6242IRGZR
✅ Drop-In✓ Em estoque
$18.25 / unidade
Ver ficha técnica →ADS6243IRGZR
✅ Drop-In✓ Em estoque
$18.75 / unidade
Ver ficha técnica →ADS6244IRGZRG4
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS6245IRGZR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS6129IRGZ25
✅ Drop-In✓ Em estoque
$23.1 / unidade
Ver ficha técnica →ADS6224IRGZ25 Classificações máximas e características elétricas
| Resolução | 12 bits |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate (max) | 105 MSPS per channel |
| Sample Rate (family max) | 125 MSPS |
| Architecture | Pipelined |
| Input Type | Differential, analog |
| Output Interface | Serialized LVDS (1-wire or 2-wire) |
| Analog Supply Voltage (AVDD) | 1.8 V |
| LVDS Supply Voltage (LVDDR) | 3.3 V |
| Reference | Internal (with external reference input option) |
| Programmable Gain | 3.5 dB coarse + 6 dB fine gain |
| Missing Codes | None (12-bit guaranteed) |
| Faixa de temperatura de operação | -40 °C to +85 °C (industrial) |
| Encapsulamento | 48-VQFN (RGZ) 7x7 mm with exposed thermal pad |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
Configuração de pinos do ADS6224IRGZ25
| Pino 1 | AVDD — Analog 1.8 V supply |
| Pino 2 | AGND — Analog ground |
| Pino 3 | INP_A — Channel A positive analog input |
| Pino 4 | INN_A — Channel A negative analog input |
| Pino 5 | AGND — Analog ground |
| Pino 6 | VCM_A — Channel A common-mode voltage |
| Pino 7 | AVDD — Analog 1.8 V supply |
| Pino 8 | AGND — Analog ground |
| Pino 9 | INP_B — Channel B positive analog input |
| Pino 10 | INN_B — Channel B negative analog input |
| Pino 11 | AGND — Analog ground |
| Pino 12 | VCM_B — Channel B common-mode voltage |
| Pino 13 | REF — Reference voltage input/output |
| Pino 14 | REFT — Reference decoupling top |
| Pino 15 | REFB — Reference decoupling bottom |
| Pino 16 | REFM — Reference mid-rail |
| Pino 17 | AVDD — Analog 1.8 V supply |
| Pino 18 | AGND — Analog ground |
| Pino 19 | RESET — Hardware reset (active low) |
| Pino 20 | PDN — Power down (active high) |
| Pino 21 | SCLK — SPI clock |
| Pino 22 | SDATA — SPI data |
| Pino 23 | SDEN — SPI enable (active low) |
| Pino 24 | MODE — Output mode select (1-wire/2-wire LVDS) |
| Pino 25 | CLKP — Differential clock input positive |
| Pino 26 | CLKM — Differential clock input negative |
| Pino 27 | AVDD — Analog 1.8 V supply |
| Pino 28 | AGND — Analog ground |
| Pino 29 | NC — Not connected (per datasheet) |
| Pino 30 | NC — Not connected (per datasheet) |
| Pino 31 | DLVDS — LVDS supply 3.3 V |
| Pino 32 | DGND — Digital ground |
| Pino 33 | OUTAP — Channel A LVDS output positive |
| Pino 34 | OUTAN — Channel A LVDS output negative |
| Pino 35 | DLVDS — LVDS supply 3.3 V |
| Pino 36 | DGND — Digital ground |
| Pino 37 | OUTBP — Channel B LVDS output positive |
| Pino 38 | OUTBN — Channel B LVDS output negative |
| Pino 39 | DLVDS — LVDS supply 3.3 V |
| Pino 40 | DGND — Digital ground |
| Pino 41 | OUTCLK_P — LVDS clock output positive |
| Pino 42 | OUTCLK_N — LVDS clock output negative |
| Pino 43 | DLVDS — LVDS supply 3.3 V |
| Pino 44 | DGND — Digital ground |
| Pino 45 | DLVDS — LVDS supply 3.3 V |
| Pino 46 | DGND — Digital ground |
| Pino 47 | DLVDS — LVDS supply 3.3 V |
| Pino 48 | DGND — Digital ground |
Aplicações típicas
ADS6224IRGZ25 é adequado para 6 aplicaçãos: Communications Base-Station Receiver, Medical Ultrasound Beamformer, Defense & Instrumentation Data Acquisition, Wireless Multi-Channel Infrastructure, Dual-Channel IF Sampling Module, Industrial Process Control Signal Acquisition.
Communications Base-Station Receiver
The ADS6224IRGZ25 is well-suited for multi-carrier GSM/LTE/WCDMA base-station receiver IF sampling where two matched 12-bit channels digitize I and Q paths. Its 105 MSPS per channel comfortably handles 20 MHz LTE carriers with adequate margin for adjacent-channel rejection, while the serialized LVDS output reduces parallel-routing congestion on the board. The 1.8 V analog supply and dual-channel integration also help shrink the BOM versus two single-channel ADCs with separate references.
Recomendado
Medical Ultrasound Beamformer
In mid-tier ultrasound beamformer front-ends, the ADS6224IRGZ25 digitizes two channels at up to 105 MSPS, supporting 16-to-32-element phased-array probe multiplexing schemes. Its 12-bit resolution suits B-mode imaging at 40-60 dB dynamic range, and the LVDS interface keeps board density manageable inside compact handle assemblies. Dual simultaneous sampling ensures the matched time delay across I/Q acquisition paths required for accurate beam steering.
Recomendado
Defense & Instrumentation Data Acquisition
The ADS6224IRGZ25 serves in defense and test-and-measurement data-acquisition modules where dual matched channels digitize IF frequencies up to ~50 MHz with 12-bit amplitude resolution. The industrial -40 °C to +85 °C operating range ensures reliable operation in field-deployable chassis, and the serialized LVDS output minimizes radiated emissions — a key consideration for EMI-sensitive ISR and electronic-warfare subsystems.
Recomendado
Wireless Multi-Channel Infrastructure
In multi-antenna wireless infrastructure such as small-cell and picocell radios, the ADS6224IRGZ25 provides dual 12-bit channel digitization at 105 MSPS for diversity/MIMO digitizing stages. Its compact 48-VQFN footprint and low ~320 mW per channel dissipation reduce board thermal load, while serialized LVDS output routing keeps PCB trace counts tractable in tight 4-layer radio modules serving 4G/5G small cells.
Recomendado
Dual-Channel IF Sampling Module
The ADS6224IRGZ25 is purpose-built for dual-channel IF sampling where I and Q baseband or intermediate-frequency signals are digitized simultaneously with matched gain. Its simultaneous sample-and-hold eliminates timing skew between I/Q paths critical for vector signal analyzer accuracy, and the internal/external reference option lets designers tie the ADC to a shared system reference for absolute amplitude accuracy across multiple channels.
Recomendado
Industrial Process Control Signal Acquisition
In high-speed industrial process control modules such as vibration monitoring on rotating machinery, the ADS6224IRGZ25 digitizes two accelerometer/IEPE channels at 105 MSPS for spectrum analysis and bearing-fault detection. Its industrial temperature range and serialized LVDS interface suit deployment near motors and pumps, while the dual-channel integration halves board real-estate versus discrete single-channel solutions in DIN-rail or PLC form factors.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ADS6224IRGZ25 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ADS6242IRGZR | ADS6243IRGZR | ADS6244IRGZRG4 | ADS6245IRGZR | ADS6129IRGZ25 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm |
| Resolution | 12 bits | 12 bits | 14 bits | 14 bits | 14 bits | 12 bits |
| Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Sample Rate (max per channel) | 105 MSPS | 65 MSPS | 80 MSPS | 105 MSPS | 125 MSPS | 105 MSPS |
| Output Interface | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| LVDS Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Reference | Internal / External | Internal / External | Internal / External | Internal / External | Internal / External | Internal / External |
Principais diferenciais
- Same-package family continuity across 12-/14-bit and 65-125 MSPS (vs ADS6244IRGZRG4)
- Serialized LVDS reduces pin count vs parallel-CMOS competitors (vs ADS62P48IRGC25 (4-channel))
- Industrial -40 °C to +85 °C operating range (vs ADS6129IRGZ25)
Notas de projeto
Decouple AVDD (1.8 V) and LVDDR (3.3 V) supplies independently with a 1 µF X7R ceramic in parallel with a 100 nF NP0/C0G ceramic placed within 5 mm of the respective supply pins. Route the analog and digital power planes as separate islands joined at a single point under the exposed thermal pad to prevent digital switching currents from coupling into the analog supply through the ground-return path.
Solder the exposed thermal pad (EP) directly to a continuous solid ground plane on the top PCB layer to provide a low-thermal-resistance path for internal dissipation (~320 mW per channel at 105 MSPS). Estimate: at +85 °C ambient and 700 mW total, junction temperature rise above ambient is approximately 30-40 °C with proper EP soldering — well within the 125 °C junction limit.
Route the LVDS output pairs (OUTAP/OUTAN, OUTBP/OUTBN, OUTCLK_P/OUTCLK_N) as 100 Ω differential microstrip with intra-pair length-matching within 150 ps (~25 mm at typical FR4 propagation) and keep the pair symmetric over a continuous reference plane. Keep LVDS traces away from the analog input pins (INP_A/INN_A, INP_B/INN_B) and the clock inputs (CLKP/CLKM) to avoid coupling noise back into the analog front-end.
Do not float the RESET or PDN pins — both must be driven actively (pull-up or driven high by the host) to ensure deterministic startup. The CLKP/CLKM differential clock must be low-jitter (<500 fs RMS) and AC-coupled with 0.1 µF caps for proper sampling; use a clock-cleaner/jitter-cleaner such as LMK04828 upstream of the ADC clock pin.
Informações de conformidade
RoHS compliant per TI product page. AEC-Q100 not applicable for industrial-grade dual ADC; automotive users should consider the dedicated ADS62x4-Q1 variants.
