ADS901E/1KG4 - 10-Bit 20MSPS 3V Pipelined ADC | Texas Instruments
N.º da peça: ADS901E/1KG4 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $7.42 | $7,42 |
| 10 | $6.68 | $66,80 |
| 100 | $5.61 | $561,00 |
| 500 | $4.85 | $2.425,00 |
| 1.000 | $4.12 | $4.120,00 |
ADS901E/1KG4 Visão geral
A pipelined ADC is a high-speed converter architecture that uses multiple low-resolution flash stages connected in series, with each stage resolving a portion of the input on successive clock cycles. The pipelined topology (ADC -> pipelined ADC -> high-speed data converter -> data acquisition IC -> signal chain IC) is the dominant choice for sample rates from 5 MSPS to several hundred MSPS because it balances resolution, speed, and power efficiency. The ADS901 belongs to TI's SpeedPlus family, optimized for low-voltage, low-power applications such as portable imaging, digital communication basebands, and consumer video.
Key features include 10-bit resolution, 20 MSPS maximum sample rate, 3V single-supply operation, an industrial -40C to +85C temperature range, and a pipelined converter type. The parallel CMOS-compatible output interface simplifies connection to ASICs, FPGAs, and DSPs. The wide-bandwidth track/hold front end preserves signal integrity well beyond the Nyquist frequency, and the full-scale input range is set by external reference resistors to optimize dynamic range for a given signal source.
Typical applications include digital still cameras, digital video camcorders, set-top box video digitizers, communications baseband processing, and portable test equipment. The 3V supply and 60 mW power make it particularly attractive for battery-powered or thermally constrained designs where high-speed conversion is required without the bulk of a 5V analog front end.
When designing with the ADS901, ensure the analog input is AC-coupled or level-shifted to remain within the input common-mode range, and place the external reference decoupling capacitors as close to the REF pin as possible. Use a continuous ground plane under the device to minimize digital feedthrough into the analog section, and follow TI's recommended layout in the datasheet for optimal SFDR performance. This page synthesizes distributor pricing, drop-in alternatives, and design notes not found on a typical distributor listing.
Alternativas drop-in para ADS901E/1KG4 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ADS901E/1KG4 (mesmo formato e footprint) — diferindo em Package, Input Type, Architecture, Sample Rate, RoHS Status.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ADS901E/1K
✅ Drop-In✓ Em estoque
$2.59 / unidade
Ver ficha técnica →ADS902E/1KG4
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS900E/1KG4
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS901E/1K
✅ Drop-In✓ Em estoque
$2.59 / unidade
Ver ficha técnica →ADS901E/1KG4G4
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS902E
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS901E/1KG4 Classificações máximas e características elétricas
| Resolução | 10 bit |
| Number of Inputs | 1 |
| Sample Rate | 20 MSPS |
| Converter Type | Pipelined (SpeedPlus) |
| Tensão de alimentação | +3 V (nominal) |
| Input Configuration | Single-Ended or Differential |
| Data Interface | Parallel |
| Encapsulamento | 28-SSOP (5.30 mm body width) |
| Tipo de montagem | Surface Mount |
| Temperatura de operação | -40C to +85C (Industrial) |
| Temperature Grade | Industrial |
| Power Dissipation | 60 mW (typical at 20 MSPS) |
| Terminal Form | Gull Wing |
| Number of Terminals | 28 |
| Package Code | SSOP |
| Packaging | Tape & Reel (TR) |
| Status RoHS | Compliant |
| Architecture | Track/Hold + 10-bit quantizer |
Configuração de pinos do ADS901E/1KG4
| Pino 1 | AVDD — Analog supply (+3V) |
| Pino 2 | IN — Analog input (single-ended or one side of differential) |
| Pino 3 | INB — Complementary analog input (differential mode) |
| Pino 4 | REFT — Top reference decoupling |
| Pino 5 | REFB — Bottom reference decoupling |
| Pino 6 | REFIO — Reference input/output |
| Pino 7 | AGND — Analog ground |
| Pino 8 | OE — Output enable (active low) |
| Pino 9 | CLK — Sample clock input |
| Pino 10 | DVDD — Digital supply (+3V) |
| Pino 11 | DGND — Digital ground |
| Pino 12 | D9 — Data output bit 9 (MSB) |
| Pino 13 | D8 — Data output bit 8 |
| Pino 14 | D7 — Data output bit 7 |
| Pino 15 | D6 — Data output bit 6 |
| Pino 16 | D5 — Data output bit 5 |
| Pino 17 | D4 — Data output bit 4 |
| Pino 18 | D3 — Data output bit 3 |
| Pino 19 | D2 — Data output bit 2 |
| Pino 20 | D1 — Data output bit 1 |
| Pino 21 | D0 — Data output bit 0 (LSB) |
| Pino 22 | NC — Not connected (per datasheet) |
| Pino 23 | PWDN — Power-down input |
| Pino 24 | STBY — Standby input |
| Pino 25 | NC — Not connected (per datasheet) |
| Pino 26 | NC — Not connected (per datasheet) |
| Pino 27 | NC — Not connected (per datasheet) |
| Pino 28 | AVDD — Analog supply (+3V) |
Aplicações típicas
ADS901E/1KG4 é adequado para 7 aplicaçãos: Digital Still Camera Image Pipeline, Digital Video Camcorder ADC, Communications Baseband Receiver, Set-Top Box Video Digitizer, Portable Test and Measurement Front-End, Industrial Ultrasound Imaging Receive Channel, Embedded Vision and Machine Vision Digitizer.
Digital Still Camera Image Pipeline
The ADS901E/1KG4 digitizes the analog output of the CCD/CIS sensor front-end at up to 20 MSPS with 10-bit resolution, providing enough headroom for color interpolation and gamma correction. Its 3V supply and 60 mW power consumption suit compact camera designs where battery life and thermal budget are constrained. The wide-bandwidth track/hold preserves high-frequency detail, and the parallel CMOS interface connects directly to the image signal processor. Place 0.1uF and 10uF decoupling close to AVDD/DVDD, and follow a continuous ground plane to minimize digital switching noise coupling into the analog input.
Recomendado
Digital Video Camcorder ADC
The ADS901E/1KG4 digitizes composite or component analog video at 20 MSPS, sufficient for SD video digitizer applications and the front end of some progressive-scan DVD recorders. The 10-bit quantizer preserves luminance and chroma dynamic range for downstream color-space conversion. The pipelined architecture delivers one sample per clock, simplifying timing closure against the video line-locked clock. Use a differential analog front-end for best common-mode rejection, and route the parallel output bus with matched-length traces to the encoder ASIC.
Recomendado
Communications Baseband Receiver
The ADS901E/1KG4 digitizes the I or Q baseband signal at 20 MSPS in narrowband or short-range wireless receivers operating in the sub-2 GHz band. The 3V single-supply and 60 mW dissipation match the power budget of handheld radio designs. The pipelined core delivers one conversion per clock with deterministic latency, which is critical for receiver channel equalization. Drive the input differentially from a baseband op-amp output to maximize SFDR, and provide a clean 2.0V external reference for full-scale calibration.
Recomendado
Set-Top Box Video Digitizer
Inside a set-top box or video capture card, the ADS901E/1KG4 converts the baseband analog video input into a 10-bit digital stream for MPEG encoding or display processing. The 20 MSPS rate covers SD resolutions with margin for video pre-processing. The 28-SSOP package fits standard capture card layouts, and the parallel interface plugs into common video decoder ASICs. Use a low-jitter crystal oscillator to drive the sample clock and meet the 10-bit SNR floor at full input bandwidth.
Recomendado
Portable Test and Measurement Front-End
Handheld oscilloscope, data-acquisition, or signal-analyzer front-ends use the ADS901E/1KG4 to digitize input signals at 20 MSPS with 10-bit resolution. The 3V supply enables battery-powered designs and the 60 mW dissipation keeps thermal design simple. The pipelined architecture delivers real-time sample conversion with deterministic latency, suitable for trigger and time-base circuits. Add a differential input driver and an anti-alias filter ahead of the ADC to maximize usable bandwidth.
Recomendado
Industrial Ultrasound Imaging Receive Channel
In single-channel or low-channel-count ultrasound receive paths, the ADS901E/1KG4 digitizes the conditioned echo signal at 20 MSPS, which covers shallow-depth imaging modes. The industrial -40C to +85C temperature grade handles the demanding environmental profile of medical or industrial imaging equipment. The pipelined core provides a deterministic sample rate for matched-filter beamforming in the digital domain. Power-supply rejection is high enough to allow direct connection to a switching pre-regulator, provided adequate decoupling is used at the device pins.
Recomendado
Embedded Vision and Machine Vision Digitizer
Compact machine-vision modules use the ADS901E/1KG4 to convert the analog output of a line-scan or area-scan sensor into a 10-bit digital stream for downstream FPGA or DSP processing. The 3V supply, 60 mW dissipation, and 28-SSOP package fit the form factor of small industrial cameras and embedded vision cards. The pipelined architecture delivers deterministic latency, simplifying time-of-flight and 3D-vision pipelines. Use a synchronous FIFO on the digital side to absorb the high-speed parallel data bursts into the processor's slower interface.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ADS901E/1KG4 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ADS901E/1K | ADS902E/1KG4 | ADS900E/1KG4 | ADS901E | ADS901E/1KG4G4 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 28-SSOP | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Sample Rate | 20 MSPS | 20 MSPS | 30 MSPS | 20 MSPS | 20 MSPS | 20 MSPS |
| Supply Voltage | +3 V | +3 V | +3 V | +5 V | +3 V | +3 V |
| Power Dissipation | 60 mW | 60 mW | 85 mW | 75 mW | 60 mW | 60 mW |
| Converter Type | Pipelined (SpeedPlus) | Pipelined (SpeedPlus) | Pipelined (SpeedPlus) | Pipelined (SpeedPlus) | Pipelined (SpeedPlus) | Pipelined (SpeedPlus) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Data Interface | Parallel | Parallel | Parallel | Parallel | Parallel | Parallel |
| RoHS Status | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant (green) |
Principais diferenciais
- 30 MSPS upgrade available in same footprint (vs ADS902E/1KG4)
- Industrial -40C to +85C temperature grade (vs ADS901E/1K (commercial grade))
- Tape & Reel packaging with full traceability (vs ADS901E (bulk pack))
Notas de projeto
Use separate AVDD and DVDD supplies decoupled with a ferrite bead, or derive both from a clean +3V rail with a low-noise LDO such as the TPS7A4701RGWR. Place 0.1uF and 10uF ceramic capacitors as close as possible to each supply pin. Estimated: at 20 MSPS the ADC draws about 20 mA from AVDD plus 5 mA from DVDD; verify headroom on the upstream regulator during worst-case input conditions.
Use a continuous, unbroken ground plane under the device to provide a low-impedance return path for the high-speed digital output bus. Keep the analog input trace short, surrounded by ground, and routed away from the parallel digital outputs to minimize digital feedthrough. Place the REFT and REFB decoupling capacitors within 50 mils of the device pins. Following these rules preserves the rated SFDR and SNR.
Avoid driving the analog input beyond the input common-mode range specified in the datasheet; overdrive can cause long-term damage or input stage saturation that persists across conversions. Do not leave the PWDN or STBY pins floating - tie them to the active level with a defined logic level. Verify the sample clock is a low-jitter source: at 10 bits of resolution, total integrated jitter should be kept below 2-3 ps RMS to avoid degrading the SNR floor.
Series-terminate the 10-bit parallel data bus near the ADC to suppress reflections, especially when traces exceed 25 mm or when the bus connects to an ASIC on a different power plane. Use the OE pin to tri-state the bus during board test or to share the bus with another peripheral. Confirm setup and hold times against the receiver ASIC's timing specification.
Informações de conformidade
RoHS and REACH compliance per TI product page; lead-free / halogen-free / green packaging denoted by G4 suffix family. The /1KG4 suffix denotes Tape & Reel (TR). Not AEC-Q100 qualified; not suitable for automotive safety-critical applications.