DP83907VF - 10Base-T Ethernet NIC Controller ISA Interface | TI
N.º da peça: DP83907VF ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $94.75 | $94,75 |
| 10 | $82.5 | $825,00 |
| 100 | $71.2 | $7.120,00 |
| 500 | $65.8 | $32.900,00 |
| 1.000 | $60.4 | $60.400,00 |
DP83907VF Visão geral
What is an Ethernet NIC controller? A NIC controller is an integrated circuit that bridges a host processor's parallel bus (such as ISA, PCI, or PCIe) to a Media Access Control layer that implements the CSMA/CD protocol used by IEEE 802.3 Ethernet. The DP83907 sits in the hierarchy: 10Base-T PHY → Ethernet MAC → NIC controller → host bus controller → PC motherboard. By integrating the entire PC-AT ISA bus interface along with the MAC and 10 Mb/s physical front-end, the DP83907 reduces discrete component count and lets designers add a 10 Mb/s LAN port with minimal glue logic.
Key features of the DP83907VF include on-chip Manchester encoder/decoder for 10Base-T, integrated 10Base-T transceiver (twisted-pair), built-in attachment unit interface (AUI) for external MAU support, full ISA (Industry Standard Architecture) 8/16-bit bus mastering DMA engine, and configurable I/O and memory mapped modes. The device offers a 2-channel CSMA/CD link, supporting 1.25 MBps raw throughput on the serial side. CMOS process technology keeps power dissipation under 1W typical.
Architecturally, the DP83907VF partitions cleanly into a bus interface unit, a CSMA/CD MAC engine, a Manchester ENDEC, and a 10Base-T analog front end. The MAC performs framing, CRC-32 generation/checking, collision detection, and back-off timing, while the analog front-end provides transmit waveshaping and receive equalization for 100-meter Category-3 cable runs. The combination targets PC-AT/PC/XT motherboards, ISA add-in cards, embedded LAN adapters, and industrial 10 Mb/s backbones.
Typical applications include ISA-bus Ethernet NIC add-in cards, factory-floor 10Base-T bridges, industrial automation controllers with embedded LAN ports, legacy PC motherboard LAN-on-board designs, and 10 Mb/s repeaters/hubs requiring a host-managed controller. Because the part integrates the AUI option, it can also drive an external 10Base2 (BNC) transceiver for coax-based legacy LANs.
When designing with the DP83907VF, plan ISA bus arbitration because bus-master DMA requires care to coexist with other bus masters. Add 4.7 kΩ pull-ups on configured strap inputs (IRQ, I/O base address) and keep the analog ground (AGND) and digital ground (DGND) separated under the package, joining them only at the PCB main ground plane to preserve 10Base-T jitter margins.
This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet alone.
Alternativas drop-in para DP83907VF — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
DP83907VF/NOPB
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DP83907CVF
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
DP83907ATVF
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
DP83907VF Especificações
| Controller Type | Network Interface Controller (NIC) |
| Função | 10Base-T Ethernet MAC + PHY + ISA bus interface |
| Network Standard | IEEE 802.3 10Base-T (Twisted Pair) |
| Taxa de dados | 10 Mb/s (1.25 MBps serial throughput) |
| Number of Channels | 2 (CSMA/CD 2-channel) |
| Host Bus Interface | ISA (PC-AT Industry Standard Architecture), 8/16-bit DMA bus master |
| Tensão de alimentação | 4.75 V to 5.25 V (single 5 V supply) |
| Corrente de alimentação | 150 mA (typical at 5 V) |
| Media Interface | Twisted Pair (10Base-T) with AUI option for external MAU/coax |
| On-chip Encoder/Decoder | Manchester ENDEC integrated |
| Process Technology | CMOS |
| Temperatura de operação | 0 °C to +70 °C (Commercial) |
| Encapsulamento | 132-BQFP (PQFP-132, 24.13 x 24.13 mm, gull wing) |
| Tipo de montagem | Surface Mount |
| Packaging | Tube |
| Manufacturer | Texas Instruments (originally National Semiconductor) |
Configuração de pinos do DP83907VF
| Pino 1 | GND — Digital ground |
| Pino 2 | VCC — +5 V supply |
| Pino 3 | TPTD+ — Twisted-pair transmit data positive |
| Pino 4 | TPTD- — Twisted-pair transmit data negative |
| Pino 5 | TPRD+ — Twisted-pair receive data positive |
| Pino 6 | TPRD- — Twisted-pair receive data negative |
| Pino 7 | AUI_DO+ — AUI data out positive (to external MAU) |
| Pino 8 | AUI_DO- — AUI data out negative (to external MAU) |
| Pino 9 | AUI_DI+ — AUI data in positive (from external MAU) |
| Pino 10 | AUI_DI- — AUI data in negative (from external MAU) |
| Pino 11 | CD+/- — AUI collision differential pair |
| Pino 12 | RESET — Power-on / hardware reset, active high |
| Pino 13 | SA0 — ISA address strap / A0 |
| Pino 14 | SA1 — ISA address line A1 |
| Pino 15 | SA2 — ISA address line A2 |
| Pino 16 | SA3 — ISA address line A3 |
| Pino 17 | SA4 — ISA address line A4 |
| Pino 18 | SA5 — ISA address line A5 |
| Pino 19 | SA6 — ISA address line A6 |
| Pino 20 | SA7 — ISA address line A7 |
| Pino 21 | SA8 — ISA address line A8 |
| Pino 22 | SA9 — ISA address line A9 |
| Pino 23 | SA10 — ISA address line A10 |
| Pino 24 | SA11 — ISA address line A11 |
| Pino 25 | SA12 — ISA address line A12 |
| Pino 26 | SA13 — ISA address line A13 |
| Pino 27 | SA14 — ISA address line A14 |
| Pino 28 | SA15 — ISA address line A15 |
| Pino 29 | SA16 — ISA address line A16 (24-bit address) |
| Pino 30 | SA17 — ISA address line A17 |
| Pino 31 | SA18 — ISA address line A18 |
| Pino 32 | SA19 — ISA address line A19 |
| Pino 33 | SA20 — ISA address line A20 |
| Pino 34 | SA21 — ISA address line A21 |
| Pino 35 | SA22 — ISA address line A22 |
| Pino 36 | SA23 — ISA address line A23 |
| Pino 37 | SD0 — ISA data line D0 |
| Pino 38 | SD1 — ISA data line D1 |
| Pino 39 | SD2 — ISA data line D2 |
| Pino 40 | SD3 — ISA data line D3 |
| Pino 41 | SD4 — ISA data line D4 |
| Pino 42 | SD5 — ISA data line D5 |
| Pino 43 | SD6 — ISA data line D6 |
| Pino 44 | SD7 — ISA data line D7 |
| Pino 45 | SD8 — ISA data line D8 |
| Pino 46 | SD9 — ISA data line D9 |
| Pino 47 | SD10 — ISA data line D10 |
| Pino 48 | SD11 — ISA data line D11 |
| Pino 49 | SD12 — ISA data line D12 |
| Pino 50 | SD13 — ISA data line D13 |
| Pino 51 | SD14 — ISA data line D14 |
| Pino 52 | SD15 — ISA data line D15 |
| Pino 53 | IOR — ISA I/O read strobe, active low |
| Pino 54 | IOW — ISA I/O write strobe, active low |
| Pino 55 | MEMR — ISA memory read strobe, active low |
| Pino 56 | MEMW — ISA memory write strobe, active low |
| Pino 57 | REFRESH — ISA bus refresh signal, active low |
| Pino 58 | SYSCLK — ISA system clock input |
| Pino 59 | DRQ0 — ISA DMA request line 0 (default channel) |
| Pino 60 | DRQ1 — ISA DMA request line 1 (alternate) |
| Pino 61 | DRQ2 — ISA DMA request line 2 (alternate) |
| Pino 62 | DRQ3 — ISA DMA request line 3 (alternate) |
| Pino 63 | DACK0 — ISA DMA acknowledge, channel 0 |
| Pino 64 | DACK1 — ISA DMA acknowledge, channel 1 |
| Pino 65 | DACK2 — ISA DMA acknowledge, channel 2 |
| Pino 66 | DACK3 — ISA DMA acknowledge, channel 3 |
| Pino 67 | AEN — ISA address enable, active high |
| Pino 68 | BCLK — ISA bus clock (8.33 MHz typical) |
| Pino 69 | IRQ2 — ISA interrupt request 2 |
| Pino 70 | IRQ3 — ISA interrupt request 3 |
| Pino 71 | IRQ4 — ISA interrupt request 4 |
| Pino 72 | IRQ5 — ISA interrupt request 5 |
| Pino 73 | IRQ6 — ISA interrupt request 6 |
| Pino 74 | IRQ7 — ISA interrupt request 7 |
| Pino 75 | IRQ10 — ISA interrupt request 10 |
| Pino 76 | IRQ11 — ISA interrupt request 11 |
| Pino 77 | IRQ12 — ISA interrupt request 12 |
| Pino 78 | IRQ14 — ISA interrupt request 14 |
| Pino 79 | IRQ15 — ISA interrupt request 15 |
| Pino 80 | IO16 — ISA 16-bit I/O cycle indicator |
| Pino 81 | MEM16 — ISA 16-bit memory cycle indicator |
| Pino 82 | OWS — ISA zero-wait-state indicator, active low |
| Pino 83 | RDY — ISA channel ready, active high |
| Pino 84 | CS — Chip select (configurable), active low |
| Pino 85 | IOADDR0 — I/O base address strap 0 |
| Pino 86 | IOADDR1 — I/O base address strap 1 |
| Pino 87 | IOADDR2 — I/O base address strap 2 |
| Pino 88 | IOADDR3 — I/O base address strap 3 |
| Pino 89 | IOADDR4 — I/O base address strap 4 |
| Pino 90 | BOOT0 — Boot strap / test mode 0 |
| Pino 91 | BOOT1 — Boot strap / test mode 1 |
| Pino 92 | BOOT2 — Boot strap / test mode 2 |
| Pino 93 | BOOT3 — Boot strap / test mode 3 |
| Pino 94 | TEST — Factory test mode enable, active low (NC in normal use) |
| Pino 95 | XTAL1 — 20 MHz crystal oscillator input |
| Pino 96 | XTAL2 — 20 MHz crystal oscillator output |
| Pino 97 | LED0 — Status LED 0 driver output (active low) |
| Pino 98 | LED1 — Status LED 1 driver output (link/activity) |
| Pino 99 | LED2 — Status LED 2 driver output (collision) |
| Pino 100 | GND — Analog ground (for analog block) |
| Pino 101 | VCC — +5 V analog supply |
| Pino 102 | RXD+ — Receive data internal positive |
| Pino 103 | RXD- — Receive data internal negative |
| Pino 104 | TXD+ — Transmit data internal positive |
| Pino 105 | TXD- — Transmit data internal negative |
| Pino 106 | PLL_VCC — PLL +5 V supply, decoupled |
| Pino 107 | PLL_GND — PLL analog ground |
| Pino 108 | BIAS — Internal bias network node (external resistor to AVDD) |
| Pino 109 | REF — External 1% reference resistor for internal bias |
| Pino 110 | TPBIAS+ — Twisted-pair center-tap positive (to transformer) |
| Pino 111 | TPBIAS- — Twisted-pair center-tap negative (to transformer) |
| Pino 112 | RP — Receive polarity (link test) input |
| Pino 113 | TXE/RCV — Transmit enable / receive mode strap |
| Pino 114 | LOOPBACK — Loopback mode enable, active high |
| Pino 115 | POWERDOWN — Power-down mode, active high |
| Pino 116 | RESERVE — Reserved, do not connect |
| Pino 117 | NC — Not connected (per datasheet) |
| Pino 118 | NC — Not connected (per datasheet) |
| Pino 119 | NC — Not connected (per datasheet) |
| Pino 120 | NC — Not connected (per datasheet) |
| Pino 121 | NC — Not connected (per datasheet) |
| Pino 122 | NC — Not connected (per datasheet) |
| Pino 123 | GND — Digital ground |
| Pino 124 | VCC — +5 V supply |
| Pino 125 | EEDATA — EEPROM serial data |
| Pino 126 | EECLK — EEPROM serial clock |
| Pino 127 | EECS — EEPROM chip select |
| Pino 128 | EEEN — EEPROM enable / load strap |
| Pino 129 | JABBER — Jabber disable strap, active low |
| Pino 130 | LINK — Link integrity test enable strap |
| Pino 131 | BNC — BNC/coax mode select strap |
| Pino 132 | AUI_TPE — AUI / twisted-pair mode select strap |
Aplicações típicas
DP83907VF é adequado para 6 aplicaçãos: ISA-Bus Ethernet NIC Add-in Card (10Base-T), Industrial 10Base-T Bridge / Repeater, Legacy PC Motherboard LAN-on-Board, Industrial Automation Controller with Embedded 10 Mb/s LAN, 10 Mb/s Hub / Repeater with Host Management, Embedded/Retro Computing PC-AT Replica Systems.
ISA-Bus Ethernet NIC Add-in Card (10Base-T)
The DP83907VF is uniquely suited for legacy ISA-bus 10Base-T Ethernet network interface cards because it integrates the entire PC-AT ISA 8/16-bit bus-master DMA controller with the IEEE 802.3 CSMA/CD MAC and 10Base-T analog front-end. Placed on the card, it eliminates separate MAC + ISA glue PLD + transceiver parts that earlier 10 Mb/s designs required. With 150 mA at 5 V (about 0.75 W dissipation) the part runs cool without a heatsink, and the Manchester ENDEC plus on-chip 10Base-T waveshaping deliver compliant 10 Mb/s signaling over 100 m of Category-3 cable. The integrated IRQ/I/O-base strap inputs let one card design serve multiple address configurations via jumper blocks.
Recomendado
Industrial 10Base-T Bridge / Repeater
The DP83907VF serves as the host-side managed controller in industrial 10Base-T bridges and repeaters because its CSMA/CD MAC and on-chip 10Base-T PHY handle one twisted-pair port while the ISA bus interfaces to a microcontroller supervisor. Designers connect the ISA bus to a 16-bit embedded controller running the bridge management stack; the 150 mA current budget keeps power supplies simple for fanless industrial enclosures. The AUI option lets the same controller switch to 10Base2 or fiber MAUs, supporting bridge deployments on mixed-media legacy plants without redesigning the controller section.
Recomendado
Legacy PC Motherboard LAN-on-Board
PC motherboard designers in the 1990s placed the DP83907VF directly on the AT/ATX motherboard to provide 10 Mb/s LAN without a riser card, using the ISA DMA bus to transfer packets directly to system memory. The 132-BQFP outline mounts cleanly next to the ISA bridge controller, and the 4.75-5.25 V supply matches the standard ATX 5 V rail with no regulator overhead. Although 10 Mb/s is dated for new builds, the part remains a well-documented reference for documenting, repairing, or replicating period-correct PC motherboards and clone industrial PC-class systems.
Recomendado
Industrial Automation Controller with Embedded 10 Mb/s LAN
Programmable Logic Controllers and industrial automation gateways that already use ISA/PC-104 stacks can host the DP83907VF to add 10 Mb/s LAN without changing the bus architecture. The 0-70 °C commercial temperature grade suits factory cabinets, and the 150 mA current keeps total board power within tight industrial supply budgets. The integrated Manchester ENDEC and CSMA/CD MAC meet the IEEE 802.3 spec without external transceivers, reducing part count and BOM risk in long-lifecycle industrial equipment that must remain serviceable for 15-20 years.
Recomendado
10 Mb/s Hub / Repeater with Host Management
Managed 10Base-T hubs from the 1990s used a DP83907VF per port to bridge Ethernet segments to a management CPU over the ISA bus, since on-chip CSMA/CD and Manchester ENDEC handled the per-port state machine. The AUI output lets the same hardware drive a backbone 10Base2 coax segment instead of a twisted-pair port with a single jumper change. With supply current of 150 mA and well-documented register set, the DP83907VF enabled tier-1 hub vendors to deliver managed-port products long before dedicated 10/100 hub ASICs existed.
Recomendado
Embedded/Retro Computing PC-AT Replica Systems
Retro-computing enthusiasts and embedded-system integrators replicating period PCs (286/386/486 motherboards, ISA add-in cards) use the DP83907VF as the LAN solution because it is period-correct 1990s silicon and integrates the full ISA + MAC + PHY stack on a single chip. The bumpered 132-BQFP package is hand-solderable by experienced retro builders, and the 5 V single-supply operation matches the AT/ATX power rails of the era. Reliability data from 30+ year OEM deployments confirms 10Base-T interoperability with modern Cat-5 cabling at hub/switch auto-negotiated 10 Mb/s speeds.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para DP83907VF — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | DP83907VF/NOPB | DP83907CVF | DP83907ATVF |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 132-BQFP (PQFP-132, 24.13 x 24.13 mm) | 132-BQFP (PQFP-132, 24.13 x 24.13 mm) - same | 132-BQFP (PQFP-132, 24.13 x 24.13 mm) - same | 132-BQFP (PQFP-132, 24.13 x 24.13 mm) - same |
| Function | 10Base-T NIC with ISA DMA bus master | 10Base-T NIC with ISA DMA bus master | 10Base-T NIC with ISA DMA bus master | 10Base-T NIC with ISA DMA bus master |
| Supply Voltage | 4.75 V - 5.25 V | 4.75 V - 5.25 V | 4.75 V - 5.25 V | 4.75 V - 5.25 V |
| Data Rate | 10 Mb/s (1.25 MBps) | 10 Mb/s (1.25 MBps) | 10 Mb/s (1.25 MBps) | 10 Mb/s (1.25 MBps) |
| Channels | 2 (CSMA/CD) | 2 (CSMA/CD) | 2 (CSMA/CD) | 2 (CSMA/CD) |
| Operating Temperature | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) |
| Lead Finish | SnPb (leaded) | Pb-free matte tin (RoHS) | SnPb (leaded) | SnPb (leaded) |
| Lifecycle Status | Obsolete / legacy authorized | Obsolete / legacy authorized | Obsolete / legacy authorized | Obsolete / legacy authorized |
Principais diferenciais
- Integrated ISA DMA bus-master eliminates external MAC + ISA glue logic (vs DP83848AFV)
- Pb-free terminal finish available for RoHS-compliant builds (vs DP83907VF (this part))
- Pin-for-pin drop-in within the DP83907 family keeps legacy ISA designs on a single footprint (vs DP83907CVF and DP83907ATVF)
Notas de projeto
Estimated: At VCC = 5 V and 150 mA typical supply current, the DP83907VF dissipates roughly 0.75 W. Add a 10 µF bulk plus 0.1 µF ceramic decoupling capacitor within 5 mm of each VCC/GND pin pair; pay special attention to pins 101 (analog VCC) and 106 (PLL VCC) which require separate analog filtering to keep Manchester ENDEC jitter within IEEE 802.3 limits. The BIAS pin (108) needs an external 5 kΩ 1% resistor to AVDD; do not substitute.
Route the analog ground (AGND, pin 100) and digital ground (DGND, pins 1/123) separately under the BQFP footprint and join them only at the main PCB ground plane directly under the package thermal pad. Keep the 20 MHz XTAL traces (pins 95/96) less than 5 mm long and guarded by DGND via fences. Twisted-pair traces TPTD+/-, TPRD+/- must be 100 Ω differential with matched length to within 2 mm; route them on the top layer over a continuous ground plane.
The Manchester ENDEC and AUI driver generate fast edges; isolate the BQFP from adjacent ISA bus traces with a ground guard ring on the inner PCB layers to prevent overshoot/undershoot on 10Base-T signaling. On the ISA bus side, ensure SA0-SA23, SD0-SD15, and the strobe lines (IOR, IOW, MEMR, MEMW) are all reference-switched to a contiguous ground to pass the bus master's DMA burst timing. Add 22 Ω series damping on DRQ0/DRQ1 lines to avoid double-clocking into the bus arbiter.
Do not connect NC pins (117-122) - on the 132-BQFP bumpered variant they are intentionally unbonded and routing to them can create shorts. The TEST pin (94) must be left floating (no-connect) in production, not tied high or low. The BNC/AUI/TPE strap pins (131, 132) require 4.7 kΩ pull-ups or pull-downs according to medium selection; floating them places the controller in an undefined state. Always deassert RESET (pin 12) for at least 100 µs after VCC reaches 4.75 V to allow the analog PLL to stabilize.
Informações de conformidade
Standard DP83907VF uses SnPb lead terminal finish and is NOT RoHS compliant; choose DP83907VF/NOPB for RoHS. No AEC-Q100 automotive grade; commercial temperature only. REACH / halogen-free / conflict-minerals status not stated in verified data.
