Intel

EPF6024ATC144-18 - FLEX 6000 FPGA 24K Gates 144-TQFP | Intel

Name: EPF6024ATC144-18 - FLEX 6000 FPGA 24K Gates 144-TQFP | Intel
Brand: Intel
SKU: EPF6024ATC144-18
Price: 17.8 USD
Availability: InStock

N.º da peça: EPF6024ATC144-18 ✗ Fim de vida

Em estoque Enviado em 1 a 3 dias úteis

3.3 V Vdss 144-pin TQFP (TQFP144) Package -18 Speed

A partir de $17.8 USD / unidade

MOQ: 1 |

Preço atualizado: 2026-09-11

Preços por volume

Qtd.	Preço unitário	Total
1	$28.5	$28,50
10	$25.2	$252,00
100	$22	$2.200,00
500	$19.5	$9.750,00
1.000	$17.8	$17.800,00

ℹ️ Todos os preços estão em USD

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Quantidade

EPF6024ATC144-18 Visão geral

The Intel (formerly Altera) EPF6024ATC144-18 is a member of the FLEX 6000 family of SRAM-based FPGAs, providing 24,000 typical gates, 1,960 logic elements (LEs), and 196 logic array blocks (LABs) in a 144-pin Thin Quad Flat Pack (TQFP) package with industrial-grade speed grade -18. Built on a 5V-tolerant CMOS SRAM process, the FLEX 6000 family was designed as a low-cost programmable alternative to high-volume gate-array applications, enabling rapid design changes during prototyping and pre-production.

An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit containing an array of programmable logic blocks, interconnect, and I/O cells that the designer configures after manufacturing using a hardware description language (HDL). FPGAs sit in the broader taxonomy of programmable logic devices (PLDs) and bridge the gap between fixed-function ASICs (high NRE, high volume) and discrete logic (low density, slow prototyping). Within the Altera/Intel portfolio hierarchy, FLEX 6000 devices are positioned as low-density, cost-optimized SRAM FPGAs, below the FLEX 10K family (which added embedded array blocks) and well below modern Cyclone and Stratix families.

Key features include 117 user I/O pins supporting 5V, 3.3V, and 2.5V I/O standards, a 3.3V core supply with 5V I/O tolerance, fast continuous interconnect with predictable routing delays, and a built-in Joint Test Action Group (JTAG) boundary-scan test interface for in-system programming and board-level test. The device is configured via the Altera FLEX 6000 series configuration scheme using serial or parallel configuration devices, and supports multi-device configuration chains.

The FLEX 6000 architecture uses a four-input look-up table (LUT) per logic element, with carry and cascade chains for high-speed arithmetic and wide-input functions. Each LAB contains 10 LEs and connects to the FastTrack Interconnect, an efficient continuous routing fabric that minimizes timing skew and supports high-speed designs up to the device's specified speed grade.

Typical applications include telecommunications interface bridging, industrial control glue logic, prototyping of ASIC designs, programmable I/O expansion for embedded microcontrollers, and educational platforms. The 144-TQFP package provides ample I/O for legacy peripheral interfacing while remaining hand-solderable for low-volume builds. Engineers commonly pair this device with EPC2 configuration PROMs for standalone operation.

When designing with this device, ensure the JTAG chain order matches the Quartus MAX+PLUS II or Quartus Prime device programmer configuration. Unused I/O pins should be left floating or driven to a defined state, and the global clear (DEV_CLRn) signal must be properly terminated to avoid inadvertent resets during power-up. The -18 speed grade indicates a -18 pin/pin delay relationship used for timing-driven compilation.

Alternativas drop-in para EPF6024ATC144-18 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPF6024ATC144-18 (mesmo formato e footprint) — diferindo em Package, Speed Grade, Operating Temperature, Process Technology, Configuration Memory.

EPF6024ATC144-10

Altera

Package: 144-LQFP

Speed Grade: -10

Configuration Memory: SRAM