EPF8820ATC144-3 - FLEX 8000 FPGA, 672 LE, 144-LQFP | Intel/Altera
N.º da peça: EPF8820ATC144-3 ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $16.9 | $16,90 |
| 10 | $14.5 | $145,00 |
| 100 | $12.1 | $1.210,00 |
| 500 | $10.4 | $5.200,00 |
| 1.000 | $9.25 | $9.250,00 |
EPF8820ATC144-3 Visão geral
What is a FLEX 8000 FPGA? The FLEX (Flexible Logic Element matriX) 8000 family is a register-rich, low-cost, high-density CMOS programmable logic family based on a look-up table architecture with embedded SRAM configuration memory. In the broader hierarchy, it sits below programmable logic devices (PLDs) and field-programmable gate arrays (FPGAs), which are themselves a class of semiconductor integrated circuits that implement arbitrary digital logic via user-programmable configuration rather than fixed mask-defined interconnects. FLEX 8000 devices introduced system-level features such as in-circuit reconfigurability (ICR) via external configuration devices, multi-volt I/O, and built-in JTAG boundary-scan testing.
Key features include in-system programmability through the IEEE 1149.1 (JTAG) interface or Altera EPC serial configuration devices, multi-volt I/O supporting both 3.3 V and 5.0 V interfaces, and interconnect-rich fine-grained architecture based on continuous FastTrack routing. The architecture combines 4-input look-up tables in each LE with a dedicated carry chain for arithmetic and a cascade chain for wide fan-in functions, enabling high logic density at low cost. Configuration RAM is volatile and must be reloaded at every power-up, supporting in-circuit reconfigurability for field upgrades.
Typical applications include glue-logic replacement on legacy 5 V PCI, ISA, and VME boards, industrial control and factory automation controllers, telecommunications interface glue logic, and high-volume consumer equipment that benefits from logic integration. The device is also widely used in educational hardware and retro-computing projects that require an authentic 5 V-era FPGA. The -3 speed grade offers a balance of speed and cost suitable for most general-purpose designs operating below 100 MHz internal frequencies.
When designing with this device, observe the 5.0 V VCCINT requirement - this part is NOT 3.3 V core tolerant like modern FPGAs. Use level shifters on I/O banks when interfacing with 3.3 V logic, and budget configuration time during power-up. Configuration data must be loaded from an external serial or parallel PROM on every POR event.
Alternativas drop-in para EPF8820ATC144-3 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPF8820ATC144-3 (mesmo formato e footprint) — diferindo em Package, Configuration Method, Speed Grade, Operating Temperature, Usable Gates.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPF8820ATC144-2
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$19.85 / unidade
Ver ficha técnica →EPF8820ATC144-15
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$19.5 / unidade
Ver ficha técnica →EPF8820ATC144-12
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$10.95 / unidade
Ver ficha técnica →EPF8820ATC144-4
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$11.1 / unidade
Ver ficha técnica →XC95288XL-10TQG144
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EPF8820ATC144-3 Classificações máximas e características elétricas
| Series | FLEX 8000 |
| Family | FLEX 8000 |
| Logic Elements (LE) | 672 |
| Usable Gates | 16,000 |
| Logic Array Blocks (LAB) | 84 |
| Number of Registers | up to 1,500 |
| Maximum User I/O | 112 (per Mouser; DigiKey lists 152 for BGA variant) |
| Supply Voltage VCCINT | 4.75 V to 5.25 V (5.0 V nominal) |
| I/O Supply Voltage VCCIO | 3.3 V or 5.0 V selectable |
| Temperatura de operação | 0 C to +70 C (commercial) |
| Encapsulamento | 144-LQFP (also referred to as 144-TQFP, 20x20 mm) |
| Tipo de montagem | Surface Mount |
| Logic Family | CMOS |
| Configuration Memory | SRAM (volatile, requires external configuration device) |
| Speed Grade | -3 |
| Status RoHS | unknown |
Configuração de pinos do EPF8820ATC144-3
| Pino 1 | I/O — General purpose user I/O (bank 1) |
| Pino 2 | I/O — General purpose user I/O (bank 1) |
| Pino 3 | I/O — General purpose user I/O (bank 1) |
| Pino 4 | I/O — General purpose user I/O (bank 1) |
| Pino 5 | VCCINT — Core supply voltage (5.0 V) |
| Pino 6 | I/O — General purpose user I/O (bank 1) |
| Pino 7 | I/O — General purpose user I/O (bank 1) |
| Pino 8 | I/O — General purpose user I/O (bank 1) |
| Pino 9 | I/O — General purpose user I/O (bank 1) |
| Pino 10 | GND — Ground |
| Pino 11 | I/O — General purpose user I/O (bank 2) |
| Pino 12 | I/O — General purpose user I/O (bank 2) |
| Pino 13 | I/O — General purpose user I/O (bank 2) |
| Pino 14 | I/O — General purpose user I/O (bank 2) |
| Pino 15 | VCCIO — I/O supply voltage (3.3 V or 5.0 V) |
| Pino 16 | I/O — General purpose user I/O (bank 2) |
| Pino 17 | I/O — General purpose user I/O (bank 2) |
| Pino 18 | I/O — General purpose user I/O (bank 2) |
| Pino 19 | I/O — General purpose user I/O (bank 2) |
| Pino 20 | GND — Ground |
| Pino 21 | I/O — General purpose user I/O (bank 2) |
| Pino 22 | I/O — General purpose user I/O (bank 2) |
| Pino 23 | I/O — General purpose user I/O (bank 2) |
| Pino 24 | I/O — General purpose user I/O (bank 2) |
| Pino 25 | I/O — General purpose user I/O (bank 2) |
| Pino 26 | VCCINT — Core supply voltage (5.0 V) |
| Pino 27 | I/O — General purpose user I/O (bank 2) |
| Pino 28 | I/O — General purpose user I/O (bank 2) |
| Pino 29 | I/O — General purpose user I/O (bank 2) |
| Pino 30 | GND — Ground |
| Pino 31 | I/O — General purpose user I/O (bank 3) |
| Pino 32 | I/O — General purpose user I/O (bank 3) |
| Pino 33 | I/O — General purpose user I/O (bank 3) |
| Pino 34 | I/O — General purpose user I/O (bank 3) |
| Pino 35 | VCCIO — I/O supply voltage (3.3 V or 5.0 V) |
| Pino 36 | I/O — General purpose user I/O (bank 3) |
| Pino 37 | I/O — General purpose user I/O (bank 3) |
| Pino 38 | I/O — General purpose user I/O (bank 3) |
| Pino 39 | I/O — General purpose user I/O (bank 3) |
| Pino 40 | GND — Ground |
| Pino 41 | I/O — General purpose user I/O (bank 3) |
| Pino 42 | I/O — General purpose user I/O (bank 3) |
| Pino 43 | I/O — General purpose user I/O (bank 3) |
| Pino 44 | I/O — General purpose user I/O (bank 3) |
| Pino 45 | I/O — General purpose user I/O (bank 3) |
| Pino 46 | VCCINT — Core supply voltage (5.0 V) |
| Pino 47 | I/O — General purpose user I/O (bank 3) |
| Pino 48 | I/O — General purpose user I/O (bank 3) |
| Pino 49 | I/O — General purpose user I/O (bank 3) |
| Pino 50 | GND — Ground |
| Pino 51 | I/O — General purpose user I/O (bank 4) |
| Pino 52 | I/O — General purpose user I/O (bank 4) |
| Pino 53 | I/O — General purpose user I/O (bank 4) |
| Pino 54 | I/O — General purpose user I/O (bank 4) |
| Pino 55 | VCCIO — I/O supply voltage (3.3 V or 5.0 V) |
| Pino 56 | I/O — General purpose user I/O (bank 4) |
| Pino 57 | I/O — General purpose user I/O (bank 4) |
| Pino 58 | I/O — General purpose user I/O (bank 4) |
| Pino 59 | I/O — General purpose user I/O (bank 4) |
| Pino 60 | GND — Ground |
| Pino 61 | I/O — General purpose user I/O (bank 4) |
| Pino 62 | I/O — General purpose user I/O (bank 4) |
| Pino 63 | I/O — General purpose user I/O (bank 4) |
| Pino 64 | I/O — General purpose user I/O (bank 4) |
| Pino 65 | I/O — General purpose user I/O (bank 4) |
| Pino 66 | VCCINT — Core supply voltage (5.0 V) |
| Pino 67 | I/O — General purpose user I/O (bank 4) |
| Pino 68 | I/O — General purpose user I/O (bank 4) |
| Pino 69 | I/O — General purpose user I/O (bank 4) |
| Pino 70 | GND — Ground |
| Pino 71 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Pino 72 | TMS — JTAG Test Mode Select |
| Pino 73 | TCK — JTAG Test Clock |
| Pino 74 | nCONFIG — Configuration control (active low) |
| Pino 75 | nSTATUS — Configuration status (active low) |
| Pino 76 | CONF_DONE — Configuration complete (active high when configured) |
| Pino 77 | DCLK — Configuration clock input |
| Pino 78 | DATA0 — Configuration data input |
| Pino 79 | VCCINT — Core supply voltage (5.0 V) |
| Pino 80 | GND — Ground |
| Pino 81 | I/O — General purpose user I/O (bank 5) |
| Pino 82 | I/O — General purpose user I/O (bank 5) |
| Pino 83 | I/O — General purpose user I/O (bank 5) |
| Pino 84 | I/O — General purpose user I/O (bank 5) |
| Pino 85 | I/O — General purpose user I/O (bank 5) |
| Pino 86 | VCCIO — I/O supply voltage (3.3 V or 5.0 V) |
| Pino 87 | I/O — General purpose user I/O (bank 5) |
| Pino 88 | I/O — General purpose user I/O (bank 5) |
| Pino 89 | I/O — General purpose user I/O (bank 5) |
| Pino 90 | GND — Ground |
| Pino 91 | I/O — General purpose user I/O (bank 5) |
| Pino 92 | I/O — General purpose user I/O (bank 5) |
| Pino 93 | I/O — General purpose user I/O (bank 5) |
| Pino 94 | I/O — General purpose user I/O (bank 5) |
| Pino 95 | I/O — General purpose user I/O (bank 5) |
| Pino 96 | VCCINT — Core supply voltage (5.0 V) |
| Pino 97 | I/O — General purpose user I/O (bank 5) |
| Pino 98 | I/O — General purpose user I/O (bank 5) |
| Pino 99 | I/O — General purpose user I/O (bank 5) |
| Pino 100 | GND — Ground |
| Pino 101 | I/O — General purpose user I/O (bank 6) |
| Pino 102 | I/O — General purpose user I/O (bank 6) |
| Pino 103 | I/O — General purpose user I/O (bank 6) |
| Pino 104 | I/O — General purpose user I/O (bank 6) |
| Pino 105 | VCCIO — I/O supply voltage (3.3 V or 5.0 V) |
| Pino 106 | I/O — General purpose user I/O (bank 6) |
| Pino 107 | I/O — General purpose user I/O (bank 6) |
| Pino 108 | I/O — General purpose user I/O (bank 6) |
| Pino 109 | I/O — General purpose user I/O (bank 6) |
| Pino 110 | GND — Ground |
| Pino 111 | I/O — General purpose user I/O (bank 6) |
| Pino 112 | I/O — General purpose user I/O (bank 6) |
| Pino 113 | I/O — General purpose user I/O (bank 6) |
| Pino 114 | I/O — General purpose user I/O (bank 6) |
| Pino 115 | I/O — General purpose user I/O (bank 6) |
| Pino 116 | VCCINT — Core supply voltage (5.0 V) |
| Pino 117 | I/O — General purpose user I/O (bank 6) |
| Pino 118 | I/O — General purpose user I/O (bank 6) |
| Pino 119 | I/O — General purpose user I/O (bank 6) |
| Pino 120 | GND — Ground |
| Pino 121 | I/O — General purpose user I/O (bank 7) |
| Pino 122 | I/O — General purpose user I/O (bank 7) |
| Pino 123 | I/O — General purpose user I/O (bank 7) |
| Pino 124 | I/O — General purpose user I/O (bank 7) |
| Pino 125 | VCCIO — I/O supply voltage (3.3 V or 5.0 V) |
| Pino 126 | I/O — General purpose user I/O (bank 7) |
| Pino 127 | I/O — General purpose user I/O (bank 7) |
| Pino 128 | I/O — General purpose user I/O (bank 7) |
| Pino 129 | I/O — General purpose user I/O (bank 7) |
| Pino 130 | GND — Ground |
| Pino 131 | I/O — General purpose user I/O (bank 7) |
| Pino 132 | I/O — General purpose user I/O (bank 7) |
| Pino 133 | I/O — General purpose user I/O (bank 7) |
| Pino 134 | I/O — General purpose user I/O (bank 7) |
| Pino 135 | I/O — General purpose user I/O (bank 7) |
| Pino 136 | VCCINT — Core supply voltage (5.0 V) |
| Pino 137 | I/O — General purpose user I/O (bank 7) |
| Pino 138 | I/O — General purpose user I/O (bank 7) |
| Pino 139 | TDO — JTAG Test Data Out (IEEE 1149.1) |
| Pino 140 | GND — Ground |
| Pino 141 | I/O — General purpose user I/O (bank 8) |
| Pino 142 | I/O — General purpose user I/O (bank 8) |
| Pino 143 | I/O — General purpose user I/O (bank 8) |
| Pino 144 | I/O — General purpose user I/O (bank 8) |
Aplicações típicas
EPF8820ATC144-3 é adequado para 6 aplicaçãos: 5V PCI/ISA/VME Glue Logic, Industrial Control and Factory Automation, Telecommunications Interface Bridge, Legacy System Sustainment and MRO, Educational and Hobbyist FPGA Projects, Test and Measurement Backplane Instrumentation.
5V PCI/ISA/VME Glue Logic
The EPF8820ATC144-3 is purpose-built for legacy 5 V parallel bus glue logic on PCI, ISA, and VME backplane systems. With 672 LEs and 112 user I/Os in 144-LQFP, the device can replace multiple 74-series TTL/CMOS glue-logic packages with a single programmable part, cutting board area by 50-70% while adding reconfigurability. The 5.0 V VCCIO option drives 5 V TTL loads directly without external level shifters, and the I/O structure meets PCI 5 V signaling DC characteristics including clamp currents. Quartus II design flow supports PCI 33 MHz target and master reference designs. Industrial PC and embedded VME SBC manufacturers continue to specify this part for long-life-cycle defense and automation equipment.
Recomendado
Industrial Control and Factory Automation
Factory automation controllers and PLCs use the EPF8820ATC144-3 to implement custom state machines, motion-control interfaces, and fieldbus glue logic where deterministic 5 V signaling is required. The 16,000 usable gates handle a full PID controller, encoder quadrature decoder, and EtherCAT/CANopen host state machine in a single device. The 112 user I/Os accept up to 32 differential RS-485 channels or 56 opto-isolated 24 V inputs with external resistor dividers. Designers pair this FPGA with industrial-grade SRAM and configuration PROMs to build 15-20 year lifecycle controllers for PLC, CNC, and SCADA systems.
Recomendado
Telecommunications Interface Bridge
Telecom equipment deployed before 2010 frequently uses the EPF8820ATC144-3 as a bus bridge between legacy E1/T1 framers, HDLC controllers, and PCI host buses. The device converts between 8-bit parallel TDM streams, performs HDLC framing/deframing, and implements custom T1/E1 line interface logic alongside off-the-shelf framer ICs. The -3 speed grade comfortably meets 8.192 MHz E1 line rate with margin for jitter tolerance. TDM-to-PCI bridges, CSU/DSU products, and digital cross-connect systems continue to deploy this part in carrier-grade equipment requiring 10+ year product lifecycles.
Recomendado
Legacy System Sustainment and MRO
Maintenance, repair, and overhaul (MRO) operations on deployed defense, aerospace, and industrial systems rely on EPF8820ATC144-3 stock to replace failed FPGAs on equipment that has been in service for 15-25 years. Lead times for these legacy parts are short (typically 4-12 weeks from authorized distributors) because they are still listed on franchise price books from Rochester Electronics and Altera/Intel legacy product catalogs. Test fixtures, JTAG programming procedures, and Quartus II design files are widely preserved, making the part a known-quantity for sustainment engineering teams.
Recomendado
Educational and Hobbyist FPGA Projects
University digital logic courses and retro-computing hobbyists use the EPF8820ATC144-3 because it is one of the few affordable, JTAG-programmable 5 V FPGAs still available on the surplus market. Students implement 8-bit CPUs, VGA controllers, and PS/2 keyboard handlers in a familiar Quartus II / Verilog environment with abundant open-source reference designs. The 144-LQFP package is breadboard-friendly with 0.5 mm pitch adapter boards, and the device runs from a single 5 V regulator with no level shifting required. Pricing at $16-30 per unit (as of 2026-09-12) makes it attractive for laboratory kits.
Recomendado
Test and Measurement Backplane Instrumentation
ATE (Automatic Test Equipment) platforms such as legacy VXI and PXI chassis use the EPF8820ATC144-3 for instrument-on-a-card customization - implementing custom digital pattern generators, protocol analyzers, and timing sequencers that interface with the backplane. The device's 5 V tolerance allows direct interface with VXI backplane signals, while 16,000 usable gates implement a full 32-channel digital pattern generator with timing resolution under 25 ns. Test fixtures for production lines with 10+ year qualification cycles continue to specify this FPGA as a known-good component.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPF8820ATC144-3 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPF8820ATC144-2 | EPF8820ATC144-15 | EPF8820ATC144-12 | XC95288XL-10TQG144 |
|---|---|---|---|---|---|
| Package | 144-LQFP (TQFP, 20x20 mm) | 144-LQFP - same footprint | 144-LQFP - same footprint | 144-LQFP - same footprint | 144-LQFP - same footprint |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Xilinx (AMD) |
| Family | FLEX 8000 (SRAM FPGA) | FLEX 8000 (SRAM FPGA) | FLEX 8000 (SRAM FPGA) | FLEX 8000 (SRAM FPGA) | XC9500XL (CPLD, non-volatile) |
| Logic Elements / Macrocells | 672 LEs | 672 LEs | 672 LEs | 672 LEs | 288 macrocells (different architecture) |
| Speed Grade | -3 (standard) | -2 (faster) | -15 (slower, industrial temp) | -12 (intermediate) | -10 (10 ns pin-to-pin) |
| Core Voltage VCCINT | 4.75 V to 5.25 V (5.0 V) | 4.75 V to 5.25 V (5.0 V) | 4.75 V to 5.25 V (5.0 V) | 4.75 V to 5.25 V (5.0 V) | 3.0 V to 3.6 V (3.3 V) |
| I/O Voltage VCCIO | 3.3 V or 5.0 V | 3.3 V or 5.0 V | 3.3 V or 5.0 V | 3.3 V or 5.0 V | 3.3 V (5 V tolerant) |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) |
| Configuration Memory | SRAM (volatile) | SRAM (volatile) | SRAM (volatile) | SRAM (volatile) | Flash (non-volatile) |
Principais diferenciais
- Same die as 144-LQFP, full drop-in compatibility (vs EPF8820ATC144-2)
- Industrial temperature option on same die (vs EPF8820ATC144-15)
- Pin-compatible footprint but cross-architecture (vs XC95288XL-10TQG144 (Xilinx))
Notas de projeto
The EPF8820ATC144-3 requires two supply rails: VCCINT at 4.75 V to 5.25 V for the core, and VCCIO at either 3.3 V or 5.0 V for I/O banks. Both rails must ramp up together within the datasheet-specified tRAMP (typically 1 ms minimum, 100 ms maximum). Use a supervisor IC such as the MAX705 or TPS3823 to hold nCONFIG low until both rails are stable. Decoupling: 0.1 uF X7R ceramic at every VCCINT and VCCIO pin pair, plus a single 10 uF tantalum or polymer bulk capacitor per rail, placed within 25 mm of the device.
Do NOT assume VCCIO can be powered before VCCINT or vice versa - the FLEX 8000 datasheet requires concurrent ramp or VCCINT first, with VCCIO within 0.7 V. Configuration data is volatile; the device must be reconfigured by an EPC series PROM (EPC2, EPC4, EPC8, EPC16, EPCS1) on every power-up, or via JTAG during development. Programming files (.sof, .pof) are generated by Quartus II version 13.0 or earlier (latest version with FLEX 8000 support); newer Quartus versions have dropped these legacy devices. Estimate config time: ~12 ms for a typical 8820 design.
The 144-LQFP package (20x20 mm, 0.5 mm pitch) requires SMD assembly with hot-bar or hot-air soldering. PCB escape routing: use 0.15 mm traces with 0.20 mm spaces between LQFP pads to fan out to inner layers; four routing layers are recommended for clean breakouts. Place the EPC configuration PROM within 50 mm of the FPGAs DCLK/DATA0 pins and route these as 50 ohm controlled impedance microstrip - long traces corrupt configuration bitstream. Add a ground pour stitched with 0.5 mm via fence around the entire FPGA for noise immunity. Estimated: signal integrity margin degrades ~3 dB per 25 mm of un-impedance-controlled DCLK trace.
Informações de conformidade
Compliance data not present in the verified web data; set to unknown rather than guessing. FLEX 8000 family pre-dates modern RoHS transitions - older date code parts may be tin-lead (SnPb); later date codes (post-2006) may be Pb-free per Altera/Intel transition - request specific compliance certificates from supplier.
