EPF8820ATC144-3 - FLEX 8000 FPGA, 672 LE, 144-LQFP | Intel/Altera
MPN: EPF8820ATC144-3 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $16.9 | $16.90 |
| 10 | $14.5 | $145.00 |
| 100 | $12.1 | $1,210.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.25 | $9,250.00 |
Drop-in alternatives for EPF8820ATC144-3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPF8820ATC144-2
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$19.85 / Unit
View Datasheet βEPF8820ATC144-15
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$19.5 / Unit
View Datasheet βEPF8820ATC144-12
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$10.95 / Unit
View Datasheet βEPF8820ATC144-4
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$11.1 / Unit
View Datasheet βXC95288XL-10TQG144
β Drop-Inπ Reference alternative (not in catalog)
EPF8820ATC144-3 Maximum Ratings & Electrical Characteristics
| Series | FLEX 8000 |
| Family | FLEX 8000 |
| Logic Elements (LE) | 672 |
| Usable Gates | 16,000 |
| Logic Array Blocks (LAB) | 84 |
| Number of Registers | up to 1,500 |
| Maximum User I/O | 112 (per Mouser; DigiKey lists 152 for BGA variant) |
| Supply Voltage VCCINT | 4.75 V to 5.25 V (5.0 V nominal) |
| I/O Supply Voltage VCCIO | 3.3 V or 5.0 V selectable |
| Operating Temperature | 0 C to +70 C (commercial) |
| Package | 144-LQFP (also referred to as 144-TQFP, 20x20 mm) |
| Mounting Type | Surface Mount |
| Logic Family | CMOS |
| Configuration Memory | SRAM (volatile, requires external configuration device) |
| Speed Grade | -3 |
| RoHS Status | unknown |
EPF8820ATC144-3 Pin Configuration
| Pin 1 | I/O β General purpose user I/O (bank 1) |
| Pin 2 | I/O β General purpose user I/O (bank 1) |
| Pin 3 | I/O β General purpose user I/O (bank 1) |
| Pin 4 | I/O β General purpose user I/O (bank 1) |
| Pin 5 | VCCINT β Core supply voltage (5.0 V) |
| Pin 6 | I/O β General purpose user I/O (bank 1) |
| Pin 7 | I/O β General purpose user I/O (bank 1) |
| Pin 8 | I/O β General purpose user I/O (bank 1) |
| Pin 9 | I/O β General purpose user I/O (bank 1) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β General purpose user I/O (bank 2) |
| Pin 12 | I/O β General purpose user I/O (bank 2) |
| Pin 13 | I/O β General purpose user I/O (bank 2) |
| Pin 14 | I/O β General purpose user I/O (bank 2) |
| Pin 15 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 16 | I/O β General purpose user I/O (bank 2) |
| Pin 17 | I/O β General purpose user I/O (bank 2) |
| Pin 18 | I/O β General purpose user I/O (bank 2) |
| Pin 19 | I/O β General purpose user I/O (bank 2) |
| Pin 20 | GND β Ground |
| Pin 21 | I/O β General purpose user I/O (bank 2) |
| Pin 22 | I/O β General purpose user I/O (bank 2) |
| Pin 23 | I/O β General purpose user I/O (bank 2) |
| Pin 24 | I/O β General purpose user I/O (bank 2) |
| Pin 25 | I/O β General purpose user I/O (bank 2) |
| Pin 26 | VCCINT β Core supply voltage (5.0 V) |
| Pin 27 | I/O β General purpose user I/O (bank 2) |
| Pin 28 | I/O β General purpose user I/O (bank 2) |
| Pin 29 | I/O β General purpose user I/O (bank 2) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β General purpose user I/O (bank 3) |
| Pin 32 | I/O β General purpose user I/O (bank 3) |
| Pin 33 | I/O β General purpose user I/O (bank 3) |
| Pin 34 | I/O β General purpose user I/O (bank 3) |
| Pin 35 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 36 | I/O β General purpose user I/O (bank 3) |
| Pin 37 | I/O β General purpose user I/O (bank 3) |
| Pin 38 | I/O β General purpose user I/O (bank 3) |
| Pin 39 | I/O β General purpose user I/O (bank 3) |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β General purpose user I/O (bank 3) |
| Pin 42 | I/O β General purpose user I/O (bank 3) |
| Pin 43 | I/O β General purpose user I/O (bank 3) |
| Pin 44 | I/O β General purpose user I/O (bank 3) |
| Pin 45 | I/O β General purpose user I/O (bank 3) |
| Pin 46 | VCCINT β Core supply voltage (5.0 V) |
| Pin 47 | I/O β General purpose user I/O (bank 3) |
| Pin 48 | I/O β General purpose user I/O (bank 3) |
| Pin 49 | I/O β General purpose user I/O (bank 3) |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β General purpose user I/O (bank 4) |
| Pin 52 | I/O β General purpose user I/O (bank 4) |
| Pin 53 | I/O β General purpose user I/O (bank 4) |
| Pin 54 | I/O β General purpose user I/O (bank 4) |
| Pin 55 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 56 | I/O β General purpose user I/O (bank 4) |
| Pin 57 | I/O β General purpose user I/O (bank 4) |
| Pin 58 | I/O β General purpose user I/O (bank 4) |
| Pin 59 | I/O β General purpose user I/O (bank 4) |
| Pin 60 | GND β Ground |
| Pin 61 | I/O β General purpose user I/O (bank 4) |
| Pin 62 | I/O β General purpose user I/O (bank 4) |
| Pin 63 | I/O β General purpose user I/O (bank 4) |
| Pin 64 | I/O β General purpose user I/O (bank 4) |
| Pin 65 | I/O β General purpose user I/O (bank 4) |
| Pin 66 | VCCINT β Core supply voltage (5.0 V) |
| Pin 67 | I/O β General purpose user I/O (bank 4) |
| Pin 68 | I/O β General purpose user I/O (bank 4) |
| Pin 69 | I/O β General purpose user I/O (bank 4) |
| Pin 70 | GND β Ground |
| Pin 71 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 72 | TMS β JTAG Test Mode Select |
| Pin 73 | TCK β JTAG Test Clock |
| Pin 74 | nCONFIG β Configuration control (active low) |
| Pin 75 | nSTATUS β Configuration status (active low) |
| Pin 76 | CONF_DONE β Configuration complete (active high when configured) |
| Pin 77 | DCLK β Configuration clock input |
| Pin 78 | DATA0 β Configuration data input |
| Pin 79 | VCCINT β Core supply voltage (5.0 V) |
| Pin 80 | GND β Ground |
| Pin 81 | I/O β General purpose user I/O (bank 5) |
| Pin 82 | I/O β General purpose user I/O (bank 5) |
| Pin 83 | I/O β General purpose user I/O (bank 5) |
| Pin 84 | I/O β General purpose user I/O (bank 5) |
| Pin 85 | I/O β General purpose user I/O (bank 5) |
| Pin 86 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 87 | I/O β General purpose user I/O (bank 5) |
| Pin 88 | I/O β General purpose user I/O (bank 5) |
| Pin 89 | I/O β General purpose user I/O (bank 5) |
| Pin 90 | GND β Ground |
| Pin 91 | I/O β General purpose user I/O (bank 5) |
| Pin 92 | I/O β General purpose user I/O (bank 5) |
| Pin 93 | I/O β General purpose user I/O (bank 5) |
| Pin 94 | I/O β General purpose user I/O (bank 5) |
| Pin 95 | I/O β General purpose user I/O (bank 5) |
| Pin 96 | VCCINT β Core supply voltage (5.0 V) |
| Pin 97 | I/O β General purpose user I/O (bank 5) |
| Pin 98 | I/O β General purpose user I/O (bank 5) |
| Pin 99 | I/O β General purpose user I/O (bank 5) |
| Pin 100 | GND β Ground |
| Pin 101 | I/O β General purpose user I/O (bank 6) |
| Pin 102 | I/O β General purpose user I/O (bank 6) |
| Pin 103 | I/O β General purpose user I/O (bank 6) |
| Pin 104 | I/O β General purpose user I/O (bank 6) |
| Pin 105 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 106 | I/O β General purpose user I/O (bank 6) |
| Pin 107 | I/O β General purpose user I/O (bank 6) |
| Pin 108 | I/O β General purpose user I/O (bank 6) |
| Pin 109 | I/O β General purpose user I/O (bank 6) |
| Pin 110 | GND β Ground |
| Pin 111 | I/O β General purpose user I/O (bank 6) |
| Pin 112 | I/O β General purpose user I/O (bank 6) |
| Pin 113 | I/O β General purpose user I/O (bank 6) |
| Pin 114 | I/O β General purpose user I/O (bank 6) |
| Pin 115 | I/O β General purpose user I/O (bank 6) |
| Pin 116 | VCCINT β Core supply voltage (5.0 V) |
| Pin 117 | I/O β General purpose user I/O (bank 6) |
| Pin 118 | I/O β General purpose user I/O (bank 6) |
| Pin 119 | I/O β General purpose user I/O (bank 6) |
| Pin 120 | GND β Ground |
| Pin 121 | I/O β General purpose user I/O (bank 7) |
| Pin 122 | I/O β General purpose user I/O (bank 7) |
| Pin 123 | I/O β General purpose user I/O (bank 7) |
| Pin 124 | I/O β General purpose user I/O (bank 7) |
| Pin 125 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 126 | I/O β General purpose user I/O (bank 7) |
| Pin 127 | I/O β General purpose user I/O (bank 7) |
| Pin 128 | I/O β General purpose user I/O (bank 7) |
| Pin 129 | I/O β General purpose user I/O (bank 7) |
| Pin 130 | GND β Ground |
| Pin 131 | I/O β General purpose user I/O (bank 7) |
| Pin 132 | I/O β General purpose user I/O (bank 7) |
| Pin 133 | I/O β General purpose user I/O (bank 7) |
| Pin 134 | I/O β General purpose user I/O (bank 7) |
| Pin 135 | I/O β General purpose user I/O (bank 7) |
| Pin 136 | VCCINT β Core supply voltage (5.0 V) |
| Pin 137 | I/O β General purpose user I/O (bank 7) |
| Pin 138 | I/O β General purpose user I/O (bank 7) |
| Pin 139 | TDO β JTAG Test Data Out (IEEE 1149.1) |
| Pin 140 | GND β Ground |
| Pin 141 | I/O β General purpose user I/O (bank 8) |
| Pin 142 | I/O β General purpose user I/O (bank 8) |
| Pin 143 | I/O β General purpose user I/O (bank 8) |
| Pin 144 | I/O β General purpose user I/O (bank 8) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8820ATC144-3 is suitable for 6 applications: 5V PCI/ISA/VME Glue Logic, Industrial Control and Factory Automation, Telecommunications Interface Bridge, Legacy System Sustainment and MRO, Educational and Hobbyist FPGA Projects, Test and Measurement Backplane Instrumentation.
5V PCI/ISA/VME Glue Logic
The EPF8820ATC144-3 is purpose-built for legacy 5 V parallel bus glue logic on PCI, ISA, and VME backplane systems. With 672 LEs and 112 user I/Os in 144-LQFP, the device can replace multiple 74-series TTL/CMOS glue-logic packages with a single programmable part, cutting board area by 50-70% while adding reconfigurability. The 5.0 V VCCIO option drives 5 V TTL loads directly without external level shifters, and the I/O structure meets PCI 5 V signaling DC characteristics including clamp currents. Quartus II design flow supports PCI 33 MHz target and master reference designs. Industrial PC and embedded VME SBC manufacturers continue to specify this part for long-life-cycle defense and automation equipment.
Recommended
Industrial Control and Factory Automation
Factory automation controllers and PLCs use the EPF8820ATC144-3 to implement custom state machines, motion-control interfaces, and fieldbus glue logic where deterministic 5 V signaling is required. The 16,000 usable gates handle a full PID controller, encoder quadrature decoder, and EtherCAT/CANopen host state machine in a single device. The 112 user I/Os accept up to 32 differential RS-485 channels or 56 opto-isolated 24 V inputs with external resistor dividers. Designers pair this FPGA with industrial-grade SRAM and configuration PROMs to build 15-20 year lifecycle controllers for PLC, CNC, and SCADA systems.
Recommended
Telecommunications Interface Bridge
Telecom equipment deployed before 2010 frequently uses the EPF8820ATC144-3 as a bus bridge between legacy E1/T1 framers, HDLC controllers, and PCI host buses. The device converts between 8-bit parallel TDM streams, performs HDLC framing/deframing, and implements custom T1/E1 line interface logic alongside off-the-shelf framer ICs. The -3 speed grade comfortably meets 8.192 MHz E1 line rate with margin for jitter tolerance. TDM-to-PCI bridges, CSU/DSU products, and digital cross-connect systems continue to deploy this part in carrier-grade equipment requiring 10+ year product lifecycles.
Recommended
Legacy System Sustainment and MRO
Maintenance, repair, and overhaul (MRO) operations on deployed defense, aerospace, and industrial systems rely on EPF8820ATC144-3 stock to replace failed FPGAs on equipment that has been in service for 15-25 years. Lead times for these legacy parts are short (typically 4-12 weeks from authorized distributors) because they are still listed on franchise price books from Rochester Electronics and Altera/Intel legacy product catalogs. Test fixtures, JTAG programming procedures, and Quartus II design files are widely preserved, making the part a known-quantity for sustainment engineering teams.
Recommended
Educational and Hobbyist FPGA Projects
University digital logic courses and retro-computing hobbyists use the EPF8820ATC144-3 because it is one of the few affordable, JTAG-programmable 5 V FPGAs still available on the surplus market. Students implement 8-bit CPUs, VGA controllers, and PS/2 keyboard handlers in a familiar Quartus II / Verilog environment with abundant open-source reference designs. The 144-LQFP package is breadboard-friendly with 0.5 mm pitch adapter boards, and the device runs from a single 5 V regulator with no level shifting required. Pricing at $16-30 per unit (as of 2026-09-12) makes it attractive for laboratory kits.
Recommended
Test and Measurement Backplane Instrumentation
ATE (Automatic Test Equipment) platforms such as legacy VXI and PXI chassis use the EPF8820ATC144-3 for instrument-on-a-card customization - implementing custom digital pattern generators, protocol analyzers, and timing sequencers that interface with the backplane. The device's 5 V tolerance allows direct interface with VXI backplane signals, while 16,000 usable gates implement a full 32-channel digital pattern generator with timing resolution under 25 ns. Test fixtures for production lines with 10+ year qualification cycles continue to specify this FPGA as a known-good component.
Recommended
Recommended Products Summary
Engineering reference data for EPF8820ATC144-3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8820ATC144-2 | EPF8820ATC144-15 | EPF8820ATC144-12 | XC95288XL-10TQG144 |
|---|---|---|---|---|---|
| Package | 144-LQFP (TQFP, 20x20 mm) | 144-LQFP - same footprint | 144-LQFP - same footprint | 144-LQFP - same footprint | 144-LQFP - same footprint |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Xilinx (AMD) |
| Family | FLEX 8000 (SRAM FPGA) | FLEX 8000 (SRAM FPGA) | FLEX 8000 (SRAM FPGA) | FLEX 8000 (SRAM FPGA) | XC9500XL (CPLD, non-volatile) |
| Logic Elements / Macrocells | 672 LEs | 672 LEs | 672 LEs | 672 LEs | 288 macrocells (different architecture) |
| Speed Grade | -3 (standard) | -2 (faster) | -15 (slower, industrial temp) | -12 (intermediate) | -10 (10 ns pin-to-pin) |
| Core Voltage VCCINT | 4.75 V to 5.25 V (5.0 V) | 4.75 V to 5.25 V (5.0 V) | 4.75 V to 5.25 V (5.0 V) | 4.75 V to 5.25 V (5.0 V) | 3.0 V to 3.6 V (3.3 V) |
| I/O Voltage VCCIO | 3.3 V or 5.0 V | 3.3 V or 5.0 V | 3.3 V or 5.0 V | 3.3 V or 5.0 V | 3.3 V (5 V tolerant) |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) |
| Configuration Memory | SRAM (volatile) | SRAM (volatile) | SRAM (volatile) | SRAM (volatile) | Flash (non-volatile) |
| Unit Price (USD) | $16.90 (LCSC, qty 1, 2026-09-12) | Estimated: ~$18-22 (faster grade) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Same die as 144-LQFP, full drop-in compatibility (vs EPF8820ATC144-2)
- Industrial temperature option on same die (vs EPF8820ATC144-15)
- Pin-compatible footprint but cross-architecture (vs XC95288XL-10TQG144 (Xilinx))
Design Notes
The EPF8820ATC144-3 requires two supply rails: VCCINT at 4.75 V to 5.25 V for the core, and VCCIO at either 3.3 V or 5.0 V for I/O banks. Both rails must ramp up together within the datasheet-specified tRAMP (typically 1 ms minimum, 100 ms maximum). Use a supervisor IC such as the MAX705 or TPS3823 to hold nCONFIG low until both rails are stable. Decoupling: 0.1 uF X7R ceramic at every VCCINT and VCCIO pin pair, plus a single 10 uF tantalum or polymer bulk capacitor per rail, placed within 25 mm of the device.
Do NOT assume VCCIO can be powered before VCCINT or vice versa - the FLEX 8000 datasheet requires concurrent ramp or VCCINT first, with VCCIO within 0.7 V. Configuration data is volatile; the device must be reconfigured by an EPC series PROM (EPC2, EPC4, EPC8, EPC16, EPCS1) on every power-up, or via JTAG during development. Programming files (.sof, .pof) are generated by Quartus II version 13.0 or earlier (latest version with FLEX 8000 support); newer Quartus versions have dropped these legacy devices. Estimate config time: ~12 ms for a typical 8820 design.
The 144-LQFP package (20x20 mm, 0.5 mm pitch) requires SMD assembly with hot-bar or hot-air soldering. PCB escape routing: use 0.15 mm traces with 0.20 mm spaces between LQFP pads to fan out to inner layers; four routing layers are recommended for clean breakouts. Place the EPC configuration PROM within 50 mm of the FPGAs DCLK/DATA0 pins and route these as 50 ohm controlled impedance microstrip - long traces corrupt configuration bitstream. Add a ground pour stitched with 0.5 mm via fence around the entire FPGA for noise immunity. Estimated: signal integrity margin degrades ~3 dB per 25 mm of un-impedance-controlled DCLK trace.
Compliance Information
Compliance data not present in the verified web data; set to unknown rather than guessing. FLEX 8000 family pre-dates modern RoHS transitions - older date code parts may be tin-lead (SnPb); later date codes (post-2006) may be Pb-free per Altera/Intel transition - request specific compliance certificates from supplier.
