EPM5192GM/883B - 192-Cell UV PLD, 55ns MAX 5000 PGA-84 | Altera
N.º da peça: EPM5192GM/883B ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $185 | $185,00 |
| 10 | $165 | $1.650,00 |
| 50 | $148 | $7.400,00 |
| 100 | $132 | $13.200,00 |
| 500 | $118 | $59.000,00 |
EPM5192GM/883B Visão geral
A UV-erasable PLD is a non-volatile programmable logic device whose configuration is stored in floating-gate memory cells and erased by exposing the die through a transparent quartz window to short-wave ultraviolet light. PLDs sit beneath FPGAs and CPLDs in the programmable-logic hierarchy; they implement glue logic, state machines, and decoder functions in fixed-OR / programmable-AND arrays. MAX 5000 devices specifically use CMOS EEPROM-style programming cells wrapped in a bipolar-compatible I/O structure, giving them higher density than 22V10-class devices while remaining erasable in-system via UV.
Key features include 192 logic macrocells (each combining a programmable AND array, a flip-flop, and an I/O buffer), a pin-to-pin propagation delay of 55 ns at the commercial 5 V VCC specification, and a total of 64 dedicated I/O pins plus dedicated clock, output enable, and clear inputs. The device is fabricated in 1.2 µm CMOS with an on-chip charge pump, eliminating the need for an external high-voltage programming supply. The /883B suffix indicates 883 Method 5004/5005 Class B screening, so the part is qualified to operate across the full military -55 °C to +125 °C temperature range.
Typical applications include avionic flight-control interface boards, military ground-vehicle wiring-replacement modules, naval combat-system signal conditioning, and any high-reliability platform where an in-system-reprogrammable UV device is preferred over a one-time-programmable (OTP) or mask-ROM part. The windowed ceramic PGA allows laboratory and field erasure plus re-programming cycles, which is essential for prototype debug on flight hardware.
When designing with the EPM5192GM/883B, observe the standard UV-PLD guidelines: maintain a high-frequency ground-return path, keep the ceramic body above a grounded copper pad for thermal relief, and route programming signals to the top side of the board so the device can be socketed and re-erased without depopulation. /883B variants require lot-traceability documentation and ESD precautions per MIL-STD-1686.
This page consolidates distributor pricing, same-package drop-in alternatives from the MAX 5000 family, and engineering guidance that is not aggregated on any single distributor or manufacturer datasheet page.
Alternativas drop-in para EPM5192GM/883B — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM5192GM/883B (mesmo formato e footprint) — diferindo em Package, Mounting Type, Device Type, Programming Method, Supply Voltage (VCC).
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM5192GM/883
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$125 / unidade
Ver ficha técnica →EPM5192GM-1/883B
✅ Drop-In✓ Em estoque
$195 / unidade
Ver ficha técnica →EPM5192GM-2/883B
✅ Drop-In✓ Em estoque
$195 / unidade
Ver ficha técnica →EPM5192GM-1
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$27.8 / unidade
Ver ficha técnica →EPM5192GM-2
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$92 / unidade
Ver ficha técnica →EPM5192GM/883B Classificações máximas e características elétricas
| Family | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (UV PLD) |
| Logic Cells | 192 |
| Propagation Delay (tPD) | 55 ns |
| Supply Voltage (VCC) | 5 V (typ) |
| Encapsulamento | CPGA-84 (PGA-84, ceramic, windowed) |
| Tipo de montagem | Through-Hole (PGA socket) |
| Contagem de pinos | 84 |
| I/O Pins | 64 |
| Process Technology | 1.2 µm CMOS with UV-erasable floating-gate cells |
| Programming Method | UV erasure + in-system serial programming, on-chip charge pump |
| Faixa de temperatura de operação | -55 °C to +125 °C (military, per /883B) |
| Screening Level | MIL-STD-883 Class B (Method 5004/5005) |
| AEC-Q100 | not_applicable |
Configuração de pinos do EPM5192GM/883B
| Pino A1 | I/O — User I/O pin (function per datasheet pin table) |
| Pino A2 | I/O — User I/O pin |
| Pino A3 | I/O — User I/O pin |
| Pino A4 | I/O — User I/O pin |
| Pino A5 | I/O — User I/O pin |
| Pino A6 | I/O — User I/O pin |
| Pino A7 | I/O — User I/O pin |
| Pino A8 | VCC — +5 V supply |
| Pino B1 | I/O — User I/O pin |
| Pino B2 | I/O — User I/O pin |
| Pino B3 | GND — Ground |
| Pino B4 | I/O — User I/O pin |
| Pino B5 | I/O — User I/O pin |
| Pino B6 | I/O — User I/O pin |
| Pino B7 | I/O — User I/O pin |
| Pino B8 | I/O — User I/O pin |
| Pino C1 | I/O — User I/O pin |
| Pino C2 | I/O — User I/O pin |
| Pino C3 | I/O — User I/O pin |
| Pino C4 | I/O — User I/O pin |
| Pino C5 | I/O — User I/O pin |
| Pino C6 | I/O — User I/O pin |
| Pino C7 | I/O — User I/O pin |
| Pino C8 | I/O — User I/O pin |
| Pino D1 | I/O — User I/O pin |
| Pino D2 | I/O — User I/O pin |
| Pino D3 | I/O — User I/O pin |
| Pino D4 | I/O — User I/O pin |
| Pino D5 | I/O — User I/O pin |
| Pino D6 | I/O — User I/O pin |
| Pino D7 | I/O — User I/O pin |
| Pino D8 | I/O — User I/O pin |
| Pino E1 | I/O — User I/O pin |
| Pino E2 | I/O — User I/O pin |
| Pino E3 | I/O — User I/O pin |
| Pino E4 | GND — Ground |
| Pino E5 | I/O — User I/O pin |
| Pino E6 | I/O — User I/O pin |
| Pino E7 | I/O — User I/O pin |
| Pino E8 | I/O — User I/O pin |
| Pino F1 | I/O — User I/O pin |
| Pino F2 | I/O — User I/O pin |
| Pino F3 | I/O — User I/O pin |
| Pino F4 | I/O — User I/O pin |
| Pino F5 | I/O — User I/O pin |
| Pino F6 | I/O — User I/O pin |
| Pino F7 | I/O — User I/O pin |
| Pino F8 | I/O — User I/O pin |
| Pino G1 | I/O — User I/O pin |
| Pino G2 | I/O — User I/O pin |
| Pino G3 | I/O — User I/O pin |
| Pino G4 | I/O — User I/O pin |
| Pino G5 | I/O — User I/O pin |
| Pino G6 | I/O — User I/O pin |
| Pino G7 | I/O — User I/O pin |
| Pino G8 | I/O — User I/O pin |
| Pino H1 | I/O — User I/O pin |
| Pino H2 | I/O — User I/O pin |
| Pino H3 | I/O — User I/O pin |
| Pino H4 | I/O — User I/O pin |
| Pino H5 | I/O — User I/O pin |
| Pino H6 | I/O — User I/O pin |
| Pino H7 | I/O — User I/O pin |
| Pino H8 | I/O — User I/O pin |
| Pino J1 | I/O — User I/O pin |
| Pino J2 | I/O — User I/O pin |
| Pino J3 | I/O — User I/O pin |
| Pino J4 | I/O — User I/O pin |
| Pino J5 | CLK — Dedicated clock input |
| Pino J6 | OE — Global output enable |
| Pino J7 | CLR — Global clear / asynchronous reset |
| Pino J8 | VCC — +5 V supply |
| Pino K1 | I/O — User I/O pin |
| Pino K2 | I/O — User I/O pin |
| Pino K3 | I/O — User I/O pin |
| Pino K4 | I/O — User I/O pin |
| Pino K5 | I/O — User I/O pin |
| Pino K6 | I/O — User I/O pin |
| Pino K7 | I/O — User I/O pin |
| Pino K8 | I/O — User I/O pin |
| Pino L1 | I/O — User I/O pin |
| Pino L2 | I/O — User I/O pin |
| Pino L3 | GND — Ground |
| Pino L4 | I/O — User I/O pin |
| Pino L5 | I/O — User I/O pin |
| Pino L6 | I/O — User I/O pin |
| Pino L7 | I/O — User I/O pin |
| Pino L8 | I/O — User I/O pin |
| Pino M1 | I/O — User I/O pin |
| Pino M2 | I/O — User I/O pin |
| Pino M3 | I/O — User I/O pin |
| Pino M4 | I/O — User I/O pin |
| Pino M5 | I/O — User I/O pin |
| Pino M6 | I/O — User I/O pin |
| Pino M7 | I/O — User I/O pin |
| Pino M8 | GND — Ground |
Aplicações típicas
EPM5192GM/883B é adequado para 6 aplicaçãos: Avionics Flight-Control Interface Logic, Military Ground-Vehicle Wiring Replacement, Naval Combat-System Signal Conditioning, Aerospace Prototype and Engineering-Development Boards, Industrial High-Reliability PLC Backplanes, Legacy Avionics Test Equipment.
Avionics Flight-Control Interface Logic
The EPM5192GM/883B's 192 logic cells and 64 I/O pins suit avionic flight-control interface boards that need to consolidate decoder, latch, and discrete-gate replacement functions onto a single MIL-STD-883 screened device. Its 55 ns tPD accommodates ARINC 429 and MIL-STD-1553 databus glue-logic rates without timing closure issues, while the UV-erasable window allows engineering change orders (ECOs) to be re-burned into the same part during flight-qualification testing. Compared with an FPGA, the MAX 5000 architecture is deterministic at power-up with no configuration memory, an important property for flight-control start-up latency.
Recomendado
Military Ground-Vehicle Wiring Replacement
Inside armored-vehicle electronics racks, the EPM5192GM/883B consolidates dozens of 54LS-series TTL gates into one device, reducing harness weight and connector pin count. The CPGA-84 package is mechanically rugged and tolerant of the -55 °C to +125 °C thermal envelope required by MIL-STD-810, and the /883B screening confirms the part has passed Group A/B/C/D acceptance testing. The 64 I/O count is large enough to absorb an entire encoder/decoder pair plus status-register logic on a single PLD, while the UV window keeps the design re-programmable through long field-deployment cycles.
Recomendado
Naval Combat-System Signal Conditioning
Naval combat-system signal-conditioning cards use the EPM5192GM/883B to implement Schmitt-trigger reconstruction, encoder-decoder pairs, and discrete-time state machines in a humidity- and vibration-tolerant ceramic PGA. The MAX 5000 architecture's hard-wired AND-OR array is immune to configuration-memory upset from the high-radiation / shipboard EMI environment, and the MIL-STD-883 Class B screening provides the lot traceability required for naval procurement. With 192 cells available, designers can implement multiple independent logic blocks in one device and reduce board real estate inside crowded 6U VME enclosures.
Recomendado
Aerospace Prototype and Engineering-Development Boards
The UV-transparent quartz window on the EPM5192GM/883B makes it ideal for aerospace prototype benches where the same device is erased and re-burned dozens of times during design iteration. Engineers can validate state machines, bus arbitrators, and timing chains at full military temperature range without consuming OTP parts, then freeze the final image on a windowless ceramic or plastic equivalent before flight build. The CPGA-84 socket is also convenient for in-circuit emulation on a development board, since the part can be swapped out without desoldering.
Recomendado
Industrial High-Reliability PLC Backplanes
In industrial PLC backplanes that must survive high electrical-noise and thermal-stress environments, the EPM5192GM/883B replaces banks of discrete 74LS / 74HCT glue logic with a single MIL-qualified PLD. Its 5 V CMOS core is compatible with legacy TTL backplane signaling levels, and the ceramic PGA construction tolerates the wide -55 °C to +125 °C ambient swings found in unconditioned outdoor cabinets. With 64 I/O and 192 cells, the device can implement address decoding, interrupt prioritization, and watchdog logic in one chip, reducing mean time between failures compared with discrete-gate implementations.
Recomendado
Legacy Avionics Test Equipment
Automatic test equipment (ATE) that supports older military avionics line-replaceable units (LRUs) frequently references the EPM5192GM/883B because it appears on the original equipment's qualified parts list. The MAX 5000 device provides deterministic combinational and registered logic needed to emulate legacy bus protocols, and its 84-pin PGA socket allows rapid swap-out when emulating different LRUs. The UV-erase capability also allows the same test fixture to be re-tasked for new LRU personalities without stocking a separate OTP inventory.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM5192GM/883B — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM5192GM/883 | EPM5192GM-1/883B | EPM5192GM-2/883B | EPM5192GM-1 | EPM5192GM-2 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | CPGA-84 (ceramic, windowed) | CPGA-84 (same) | CPGA-84 (same) | CPGA-84 (same) | CPGA-84 (same) | CPGA-84 (same) |
| Logic Cells | 192 | 192 | 192 | 192 | 192 | 192 |
| MIL-STD-883 Class B Screening | Yes | No (/883 only) | Yes | Yes | No (commercial) | No (commercial) |
| Operating Temperature Range | -55 °C to +125 °C | -55 °C to +125 °C | -55 °C to +125 °C | -55 °C to +125 °C | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (commercial) |
| I/O Pins | 64 | 64 | 64 | 64 | 64 | 64 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principais diferenciais
- MIL-STD-883 Class B screening on the same MAX 5190 die (vs EPM5192GM/883)
- Standard tPD grade gives the widest availability and lowest price (vs EPM5192GM-1/883B)
- UV-erasable window allows field re-programming (vs EPM5192C-2 (one-time-programmable ceramic PGA))
Notas de projeto
The UV-transparent quartz window must remain clean and unblocked to allow field erasure; covering the window with an opaque label or soldermask will prevent re-programming. Use a PGA socket with a low-profile heat sink or thermal pad beneath the ceramic body so the lid is not damaged during board rework. /883B parts require lot-traceability documents (C-of-C) and ESD handling per MIL-STD-1686 - request paperwork up front when sourcing from brokers.
Estimated: at 5 V VCC, with all 64 outputs switching simultaneously at 1 MHz CMOS load, internal dissipation is on the order of 250-300 mW. The CPGA-84 ceramic package dissipates this through the socket and PCB copper; ensure at least 1 sq-in of 2-oz copper under the device and a grounded thermal pad on the opposite side to keep the junction below +125 °C in a sealed enclosure.
Route programming signals and JTAG-like test pins to a top-side test pad rather than through buried vias, so the device can be socketed, erased with a UV lamp, and re-burned without depopulating the board. Keep VCC and GND pairs (A8/B3/E4/J8/L3/M8) bypassed with 0.1 µF ceramic plus 10 µF tantalum within 5 mm of each pin to control ground bounce on simultaneous-output transitions.
The 5 V CMOS MAX 5000 I/O drivers can produce ground bounce exceeding 1 V if many outputs switch simultaneously into a capacitive bus; series-damp each output with 22-33 Ω to limit di/dt, and provide a low-impedance ground return path on the layer immediately beneath the device. For synchronous clock distribution, drive the dedicated CLK input with a clean TTL source and avoid using it as a general-purpose I/O to preserve deterministic timing.
Informações de conformidade
MIL-STD-883 Class B screening is the primary compliance attribute for this part (Method 5004/5005). RoHS/REACH/lead-free status is not stated in the verified data - typical legacy Altera ceramic PGA parts were built with SnPb terminations and may not be RoHS compliant; confirm with the franchised broker's C-of-C before use in any RoHS-restricted program.
