EPM5192GM/883B - 192-Cell UV PLD, 55ns MAX 5000 PGA-84 | Altera
MPN: EPM5192GM/883B β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 50 | $148 | $7,400.00 |
| 100 | $132 | $13,200.00 |
| 500 | $118 | $59,000.00 |
Drop-in alternatives for EPM5192GM/883B β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM5192GM/883
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
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View Datasheet βEPM5192GM-1/883B
β Drop-Inβ In Stock
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View Datasheet βEPM5192GM-2/883B
β Drop-Inβ In Stock
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View Datasheet βEPM5192GM-1
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
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View Datasheet βEPM5192GM-2
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$92 / Unit
View Datasheet βEPM5192GM/883B Maximum Ratings & Electrical Characteristics
| Family | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (UV PLD) |
| Logic Cells | 192 |
| Propagation Delay (tPD) | 55 ns |
| Supply Voltage (VCC) | 5 V (typ) |
| Package | CPGA-84 (PGA-84, ceramic, windowed) |
| Mounting Type | Through-Hole (PGA socket) |
| Pin Count | 84 |
| I/O Pins | 64 |
| Process Technology | 1.2 Β΅m CMOS with UV-erasable floating-gate cells |
| Programming Method | UV erasure + in-system serial programming, on-chip charge pump |
| Operating Temperature Range | -55 Β°C to +125 Β°C (military, per /883B) |
| Screening Level | MIL-STD-883 Class B (Method 5004/5005) |
| AEC-Q100 | not_applicable |
EPM5192GM/883B Pin Configuration
| Pin A1 | I/O β User I/O pin (function per datasheet pin table) |
| Pin A2 | I/O β User I/O pin |
| Pin A3 | I/O β User I/O pin |
| Pin A4 | I/O β User I/O pin |
| Pin A5 | I/O β User I/O pin |
| Pin A6 | I/O β User I/O pin |
| Pin A7 | I/O β User I/O pin |
| Pin A8 | VCC β +5 V supply |
| Pin B1 | I/O β User I/O pin |
| Pin B2 | I/O β User I/O pin |
| Pin B3 | GND β Ground |
| Pin B4 | I/O β User I/O pin |
| Pin B5 | I/O β User I/O pin |
| Pin B6 | I/O β User I/O pin |
| Pin B7 | I/O β User I/O pin |
| Pin B8 | I/O β User I/O pin |
| Pin C1 | I/O β User I/O pin |
| Pin C2 | I/O β User I/O pin |
| Pin C3 | I/O β User I/O pin |
| Pin C4 | I/O β User I/O pin |
| Pin C5 | I/O β User I/O pin |
| Pin C6 | I/O β User I/O pin |
| Pin C7 | I/O β User I/O pin |
| Pin C8 | I/O β User I/O pin |
| Pin D1 | I/O β User I/O pin |
| Pin D2 | I/O β User I/O pin |
| Pin D3 | I/O β User I/O pin |
| Pin D4 | I/O β User I/O pin |
| Pin D5 | I/O β User I/O pin |
| Pin D6 | I/O β User I/O pin |
| Pin D7 | I/O β User I/O pin |
| Pin D8 | I/O β User I/O pin |
| Pin E1 | I/O β User I/O pin |
| Pin E2 | I/O β User I/O pin |
| Pin E3 | I/O β User I/O pin |
| Pin E4 | GND β Ground |
| Pin E5 | I/O β User I/O pin |
| Pin E6 | I/O β User I/O pin |
| Pin E7 | I/O β User I/O pin |
| Pin E8 | I/O β User I/O pin |
| Pin F1 | I/O β User I/O pin |
| Pin F2 | I/O β User I/O pin |
| Pin F3 | I/O β User I/O pin |
| Pin F4 | I/O β User I/O pin |
| Pin F5 | I/O β User I/O pin |
| Pin F6 | I/O β User I/O pin |
| Pin F7 | I/O β User I/O pin |
| Pin F8 | I/O β User I/O pin |
| Pin G1 | I/O β User I/O pin |
| Pin G2 | I/O β User I/O pin |
| Pin G3 | I/O β User I/O pin |
| Pin G4 | I/O β User I/O pin |
| Pin G5 | I/O β User I/O pin |
| Pin G6 | I/O β User I/O pin |
| Pin G7 | I/O β User I/O pin |
| Pin G8 | I/O β User I/O pin |
| Pin H1 | I/O β User I/O pin |
| Pin H2 | I/O β User I/O pin |
| Pin H3 | I/O β User I/O pin |
| Pin H4 | I/O β User I/O pin |
| Pin H5 | I/O β User I/O pin |
| Pin H6 | I/O β User I/O pin |
| Pin H7 | I/O β User I/O pin |
| Pin H8 | I/O β User I/O pin |
| Pin J1 | I/O β User I/O pin |
| Pin J2 | I/O β User I/O pin |
| Pin J3 | I/O β User I/O pin |
| Pin J4 | I/O β User I/O pin |
| Pin J5 | CLK β Dedicated clock input |
| Pin J6 | OE β Global output enable |
| Pin J7 | CLR β Global clear / asynchronous reset |
| Pin J8 | VCC β +5 V supply |
| Pin K1 | I/O β User I/O pin |
| Pin K2 | I/O β User I/O pin |
| Pin K3 | I/O β User I/O pin |
| Pin K4 | I/O β User I/O pin |
| Pin K5 | I/O β User I/O pin |
| Pin K6 | I/O β User I/O pin |
| Pin K7 | I/O β User I/O pin |
| Pin K8 | I/O β User I/O pin |
| Pin L1 | I/O β User I/O pin |
| Pin L2 | I/O β User I/O pin |
| Pin L3 | GND β Ground |
| Pin L4 | I/O β User I/O pin |
| Pin L5 | I/O β User I/O pin |
| Pin L6 | I/O β User I/O pin |
| Pin L7 | I/O β User I/O pin |
| Pin L8 | I/O β User I/O pin |
| Pin M1 | I/O β User I/O pin |
| Pin M2 | I/O β User I/O pin |
| Pin M3 | I/O β User I/O pin |
| Pin M4 | I/O β User I/O pin |
| Pin M5 | I/O β User I/O pin |
| Pin M6 | I/O β User I/O pin |
| Pin M7 | I/O β User I/O pin |
| Pin M8 | GND β Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5192GM/883B is suitable for 6 applications: Avionics Flight-Control Interface Logic, Military Ground-Vehicle Wiring Replacement, Naval Combat-System Signal Conditioning, Aerospace Prototype and Engineering-Development Boards, Industrial High-Reliability PLC Backplanes, Legacy Avionics Test Equipment.
Avionics Flight-Control Interface Logic
The EPM5192GM/883B's 192 logic cells and 64 I/O pins suit avionic flight-control interface boards that need to consolidate decoder, latch, and discrete-gate replacement functions onto a single MIL-STD-883 screened device. Its 55 ns tPD accommodates ARINC 429 and MIL-STD-1553 databus glue-logic rates without timing closure issues, while the UV-erasable window allows engineering change orders (ECOs) to be re-burned into the same part during flight-qualification testing. Compared with an FPGA, the MAX 5000 architecture is deterministic at power-up with no configuration memory, an important property for flight-control start-up latency.
Recommended
Military Ground-Vehicle Wiring Replacement
Inside armored-vehicle electronics racks, the EPM5192GM/883B consolidates dozens of 54LS-series TTL gates into one device, reducing harness weight and connector pin count. The CPGA-84 package is mechanically rugged and tolerant of the -55 Β°C to +125 Β°C thermal envelope required by MIL-STD-810, and the /883B screening confirms the part has passed Group A/B/C/D acceptance testing. The 64 I/O count is large enough to absorb an entire encoder/decoder pair plus status-register logic on a single PLD, while the UV window keeps the design re-programmable through long field-deployment cycles.
Recommended
Naval Combat-System Signal Conditioning
Naval combat-system signal-conditioning cards use the EPM5192GM/883B to implement Schmitt-trigger reconstruction, encoder-decoder pairs, and discrete-time state machines in a humidity- and vibration-tolerant ceramic PGA. The MAX 5000 architecture's hard-wired AND-OR array is immune to configuration-memory upset from the high-radiation / shipboard EMI environment, and the MIL-STD-883 Class B screening provides the lot traceability required for naval procurement. With 192 cells available, designers can implement multiple independent logic blocks in one device and reduce board real estate inside crowded 6U VME enclosures.
Recommended
Aerospace Prototype and Engineering-Development Boards
The UV-transparent quartz window on the EPM5192GM/883B makes it ideal for aerospace prototype benches where the same device is erased and re-burned dozens of times during design iteration. Engineers can validate state machines, bus arbitrators, and timing chains at full military temperature range without consuming OTP parts, then freeze the final image on a windowless ceramic or plastic equivalent before flight build. The CPGA-84 socket is also convenient for in-circuit emulation on a development board, since the part can be swapped out without desoldering.
Recommended
Industrial High-Reliability PLC Backplanes
In industrial PLC backplanes that must survive high electrical-noise and thermal-stress environments, the EPM5192GM/883B replaces banks of discrete 74LS / 74HCT glue logic with a single MIL-qualified PLD. Its 5 V CMOS core is compatible with legacy TTL backplane signaling levels, and the ceramic PGA construction tolerates the wide -55 Β°C to +125 Β°C ambient swings found in unconditioned outdoor cabinets. With 64 I/O and 192 cells, the device can implement address decoding, interrupt prioritization, and watchdog logic in one chip, reducing mean time between failures compared with discrete-gate implementations.
Recommended
Legacy Avionics Test Equipment
Automatic test equipment (ATE) that supports older military avionics line-replaceable units (LRUs) frequently references the EPM5192GM/883B because it appears on the original equipment's qualified parts list. The MAX 5000 device provides deterministic combinational and registered logic needed to emulate legacy bus protocols, and its 84-pin PGA socket allows rapid swap-out when emulating different LRUs. The UV-erase capability also allows the same test fixture to be re-tasked for new LRU personalities without stocking a separate OTP inventory.
Recommended
Recommended Products Summary
Engineering reference data for EPM5192GM/883B β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5192GM/883 | EPM5192GM-1/883B | EPM5192GM-2/883B | EPM5192GM-1 | EPM5192GM-2 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | CPGA-84 (ceramic, windowed) | CPGA-84 (same) | CPGA-84 (same) | CPGA-84 (same) | CPGA-84 (same) | CPGA-84 (same) |
| Logic Cells | 192 | 192 | 192 | 192 | 192 | 192 |
| Propagation Delay (tPD) | 55 ns | 55 ns (same) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| MIL-STD-883 Class B Screening | Yes | No (/883 only) | Yes | Yes | No (commercial) | No (commercial) |
| Operating Temperature Range | -55 Β°C to +125 Β°C | -55 Β°C to +125 Β°C | -55 Β°C to +125 Β°C | -55 Β°C to +125 Β°C | 0 Β°C to +70 Β°C (commercial) | 0 Β°C to +70 Β°C (commercial) |
| I/O Pins | 64 | 64 | 64 | 64 | 64 | 64 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- MIL-STD-883 Class B screening on the same MAX 5190 die (vs EPM5192GM/883)
- Standard tPD grade gives the widest availability and lowest price (vs EPM5192GM-1/883B)
- UV-erasable window allows field re-programming (vs EPM5192C-2 (one-time-programmable ceramic PGA))
Design Notes
The UV-transparent quartz window must remain clean and unblocked to allow field erasure; covering the window with an opaque label or soldermask will prevent re-programming. Use a PGA socket with a low-profile heat sink or thermal pad beneath the ceramic body so the lid is not damaged during board rework. /883B parts require lot-traceability documents (C-of-C) and ESD handling per MIL-STD-1686 - request paperwork up front when sourcing from brokers.
Estimated: at 5 V VCC, with all 64 outputs switching simultaneously at 1 MHz CMOS load, internal dissipation is on the order of 250-300 mW. The CPGA-84 ceramic package dissipates this through the socket and PCB copper; ensure at least 1 sq-in of 2-oz copper under the device and a grounded thermal pad on the opposite side to keep the junction below +125 Β°C in a sealed enclosure.
Route programming signals and JTAG-like test pins to a top-side test pad rather than through buried vias, so the device can be socketed, erased with a UV lamp, and re-burned without depopulating the board. Keep VCC and GND pairs (A8/B3/E4/J8/L3/M8) bypassed with 0.1 Β΅F ceramic plus 10 Β΅F tantalum within 5 mm of each pin to control ground bounce on simultaneous-output transitions.
The 5 V CMOS MAX 5000 I/O drivers can produce ground bounce exceeding 1 V if many outputs switch simultaneously into a capacitive bus; series-damp each output with 22-33 Ξ© to limit di/dt, and provide a low-impedance ground return path on the layer immediately beneath the device. For synchronous clock distribution, drive the dedicated CLK input with a clean TTL source and avoid using it as a general-purpose I/O to preserve deterministic timing.
Compliance Information
MIL-STD-883 Class B screening is the primary compliance attribute for this part (Method 5004/5005). RoHS/REACH/lead-free status is not stated in the verified data - typical legacy Altera ceramic PGA parts were built with SnPb terminations and may not be RoHS compliant; confirm with the franchised broker's C-of-C before use in any RoHS-restricted program.
