Altera

EPM9560RC240-15W - MAX 9000 CPLD 560 Macro Cells | Altera

N.º da peça: EPM9560RC240-15W ✗ Fim de vida

Em estoque Enviado em 1 a 3 dias úteis

4.75 V to 5.25 V Vdss 240-pin RQFP (PowerQuad) with exposed pad Package 117.6 MHz Speed

Contato para preços

MOQ: 1 |

Preço atualizado: 2026-09-13

Preços por volume

Qtd.	Preço unitário	Total
1	$0	$0,00
10	$0	$0,00
100	$0	$0,00
500	$0	$0,00
1.000	$0	$0,00

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EPM9560RC240-15W Visão geral

The Altera EPM9560RC240-15W is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates, 560 macrocells, and 191 user I/O pins in a 240-pin RQFP (PowerQuad) package. It operates from a 5.0 V supply (4.75 V to 5.25 V) with a 15 ns pin-to-pin propagation delay and supports in-system programmability (ISP) via an EEPROM-based configuration element.

A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks with a programmable interconnect matrix on a single die. In the broader hierarchy, a CPLD sits between simple PLDs (PAL/GAL) and FPGAs: it offers non-volatile configuration, deterministic timing, and instant-on operation, making it the preferred choice for glue logic, bus interfacing, and state machines. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, fabricated in advanced CMOS with EEPROM configuration cells.

Key differentiators of the EPM9560RC240-15W include its 560 macrocells (the highest density in the MAX 9000 family), 12,000 usable gates, 191 user I/O pins, and a 15 ns pin-to-pin delay. The device supports 5.0 V in-system programmability, allowing field reconfiguration without removing the part from the board. Its EEPROM-based architecture retains configuration without external boot memory, unlike SRAM-based FPGAs.

The MAX 9000 architecture uses a hierarchical interconnect scheme with logic array blocks (LABs) and a programmable interconnect array (PIA), delivering predictable, deterministic timing. Counter speeds reach up to 117.6 MHz to 144 MHz depending on speed grade. The 240-pin RQFP package with exposed pad provides a compact surface-mount footprint for high-I/O-count designs.

Typical applications include industrial control glue logic, bus bridging and protocol conversion, legacy system replacement, test and measurement instrumentation, telecommunications line cards, and military/aerospace systems requiring long-term supply and non-volatile configuration.

When designing with the EPM9560RC240-15W, ensure all VCC pins are decoupled with 0.1 uF ceramic capacitors placed close to the device, and provide a clean 5.0 V rail within the 4.75 V to 5.25 V range. The JTAG ISP interface requires a 10-pin header and proper pull-up resistors on TCK, TMS, TDI, and TDO.

This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for selection, replacement, and layout decisions.

Alternativas drop-in para EPM9560RC240-15W — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM9560RC240-15W (mesmo formato e footprint) — diferindo em Package, Family, Logic Array Blocks (LABs), RoHS Status, Supply Voltage.

EPM9560RC240-10

Altera

Package: 240-pin RQFP (PowerQuad)

Logic Array Blocks (LABs): 12

RoHS Status: ROHS3 Compliant