HI5767/4CA - 10-Bit 60MSPS ADC w/ Internal VREF | Intersil
N.º da peça: HI5767/4CA ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.75 | $1.375,00 |
| 500 | $11.5 | $5.750,00 |
| 1.000 | $10.2 | $10.200,00 |
HI5767/4CA Visão geral
What is a pipelined ADC? A pipelined analog-to-digital converter is a multi-stage converter that uses several low-resolution sub-ADCs and DACs in cascade to achieve higher overall resolution at high sampling rates. Pipelined ADCs sit between successive-approximation (SAR) ADCs and flash ADCs in the converter hierarchy, offering the best trade-off between speed, resolution, and power dissipation for sample rates between a few MSPS and a few hundred MSPS, dominating the 8-to-16-bit, 10-to-200 MSPS market.
Key features of the HI5767/4CA include selectable 20, 40, or 60 MSPS operation, integrated bandgap voltage reference, CMOS-compatible digital inputs, low-power CMOS process, and analog input bandwidth suitable for IF undersampling. The part supports single +5V analog supply operation per the datasheet, and its 28-SSOP/QSOP package provides a compact footprint for instrumentation and communications designs. The pipelined architecture delivers 10-bit resolution with no missing codes and differential nonlinearity within +/-1 LSB typical.
The CMOS sub-micron process enables the HI5767/4CA to combine wide analog input bandwidth (specifying suitability for undersampling applications above Nyquist) with low power dissipation, making it well-suited for battery-powered or thermally constrained systems. The internal reference eliminates external reference components and reduces PCB area while simplifying power-supply design.
Typical applications include digital oscilloscopes, IF sampling for communications receivers, CCD imaging front-ends, medical ultrasound front-ends, and radar/sonar baseband digitizers. The selectable sample rate (20/40/60 MSPS) lets one hardware platform cover multiple end-product SKUs without redesign.
When designing with this part, ensure analog and digital grounds are separated at the IC and joined at a single point to preserve SFDR. Decouple AVDD and DVDD independently with 0.1 uF ceramic capacitors placed as close to the pins as possible. Source-impedance matching at the analog input is critical for full-bandwidth performance.
This page synthesizes distributor pricing, drop-in-compatible alternative sources, and practical design notes not consolidated in any single manufacturer document.
Alternativas drop-in para HI5767/4CA — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com HI5767/4CA (mesmo formato e footprint) — diferindo em Architecture, Input Type, Package, RoHS Status, Sampling Rate.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
HI5766KCAZ
✅ Drop-In✓ Em estoque
$5.6 / unidade
Ver ficha técnica →HI5767/6CA
✅ Drop-In✓ Em estoque
$3.4 / unidade
Ver ficha técnica →HI5767/8CA
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS901E/1K
✅ Drop-In✓ Em estoque
$2.59 / unidade
Ver ficha técnica →ADS901E/1K
✅ Drop-In✓ Em estoque
$2.59 / unidade
Ver ficha técnica →HI5767/4CA Classificações máximas e características elétricas
| Resolução | 10 bits |
| Sampling Rate (max) | 60 MSPS (selectable 20/40/60 MSPS) |
| Number of Input Channels | 1 |
| Architecture | Pipelined CMOS |
| Voltage Reference | Internal |
| Data Output Interface | Parallel word |
| Encapsulamento / Caixa | 28-SSOP/QSOP (PDSO28) |
| Input Type | Single-ended analog input |
| Process Technology | CMOS |
| DNL | +/-1 LSB typical (pipelined 10-bit) |
| Tipo de montagem | Surface Mount |
| Contagem de pinos | 28 |
Configuração de pinos do HI5767/4CA
| Pino 1 | AGND — Analog ground return |
| Pino 2 | AVDD — Analog supply voltage |
| Pino 3 | AIN — Analog input |
| Pino 4 | VREF — Internal reference bypass (or external reference input) |
| Pino 5 | AGND — Analog ground |
| Pino 6 | AVDD — Analog supply voltage |
| Pino 7 | AGND — Analog ground |
| Pino 8 | DGND — Digital ground |
| Pino 9 | DVDD — Digital supply voltage |
| Pino 10 | CLK — Sampling clock input |
| Pino 11 | CLKB — Complementary clock (optional) |
| Pino 12 | OF — Output format / rate select |
| Pino 13 | DGND — Digital ground |
| Pino 14 | DB0 — Digital output bit 0 (LSB) |
| Pino 15 | DB1 — Digital output bit 1 |
| Pino 16 | DB2 — Digital output bit 2 |
| Pino 17 | DB3 — Digital output bit 3 |
| Pino 18 | DB4 — Digital output bit 4 |
| Pino 19 | DB5 — Digital output bit 5 |
| Pino 20 | DB6 — Digital output bit 6 |
| Pino 21 | DB7 — Digital output bit 7 |
| Pino 22 | DB8 — Digital output bit 8 |
| Pino 23 | DB9 — Digital output bit 9 (MSB) |
| Pino 24 | DR — Data ready / clock output |
| Pino 25 | OE — Output enable (active low) |
| Pino 26 | DGND — Digital ground |
| Pino 27 | DVDD — Digital supply voltage |
| Pino 28 | DGND — Digital ground |
Aplicações típicas
HI5767/4CA é adequado para 7 aplicaçãos: Digital Oscilloscope Front-End, IF Sampling for Communications Receivers, CCD / CMOS Imaging Front-End Digitizer, Medical Ultrasound Baseband Digitizer, Radar / Sonar Baseband Digitizer, Industrial Test & Measurement Instrumentation, Portable Battery-Powered Data Acquisition.
Digital Oscilloscope Front-End
The HI5767/4CA's 10-bit resolution and 60 MSPS sampling rate make it well-suited for the analog front-end of mid-bandwidth digital storage oscilloscopes capturing repetitive and single-shot transients. With an internal bandgap voltage reference the design removes an external reference IC that would otherwise occupy board space in a 4-channel scope chassis. The pipelined architecture delivers sub-LSB differential non-linearity for accurate peak-to-peak voltage measurements on rising edges. Place 0.1 uF ceramic decoupling caps adjacent to AVDD and DVDD pins and route analog inputs as 50-ohm controlled-impedance traces from the front-panel BNC attenuator path.
Recomendado
IF Sampling for Communications Receivers
Per the Intersil datasheet, the HI5767/4CA is characterized for IF undersampling applications in communications receivers. Its wide analog input bandwidth permits direct sampling of intermediate-frequency signals above Nyquist, eliminating an analog downconversion stage and reducing the receiver bill of materials. The 10-bit dynamic range handles the narrowband IF signals (e.g., 70 MHz IF in a super-heterodyne receiver) used in two-way radios and base station monitoring equipment. The CMOS process keeps power dissipation low enough for portable field-deployed radio terminals.
Recomendado
CCD / CMOS Imaging Front-End Digitizer
The HI5767/4CA digitizes the analog output of CCD line-scan or area-array image sensors in machine-vision cameras and document scanners, where its 60 MSPS throughput matches the pixel clock of megapixel imagers. Internal voltage reference stabilization simplifies the imaging system's calibration by holding gain error consistent across temperature excursions. Low CMOS power dissipation enables fanless camera head designs used in industrial inspection lines and flatbed scanners. Used in tandem with an op-amp transimpedance front-end (e.g., OPA656) it converts the CCD video signal into a 10-bit digital stream for FPGA image-pipeline processing.
Recomendado
Medical Ultrasound Baseband Digitizer
Portable diagnostic ultrasound carts and handheld POCUS devices use the HI5767/4CA to digitize the baseband (post-beamformed) analog signal at rates up to 60 MSPS, sufficient for 30 MHz probe center frequencies. Its 10-bit resolution enables dynamic range sufficient for B-mode grayscale imaging with >40 dB useful range, while the internal reference simplifies the FDA/IEC-60601 design documentation by removing an external reference component. The compact 28-SSOP/QSOP footprint allows multi-channel board layouts (8 or 16 channels) for multi-element probe head assemblies.
Recomendado
Radar / Sonar Baseband Digitizer
Marine fish-finder sonar modules and short-range radar front-ends use the HI5767/4CA at the baseband (post-downconversion) stage to convert analog return signals into a 10-bit digital stream for target detection DSP. The pipelined architecture's tolerance to Nyquist-zone aliasing makes the part suitable for undersampled IF returns downconverted from a 40 MHz IF stage. Internal VREF holds gain calibration across the wide temperature swings encountered in marine bridge installations, and the 28-SSOP/QSOP package footprint survives the conformal coating and vibration requirements of marine electronics certification.
Recomendado
Industrial Test & Measurement Instrumentation
Automated test equipment (ATE) and bench-top instrumentation including spectrum analyzers and signal analyzers employ the HI5767/4CA as the intermediate-bandwidth digitizer for input frequencies up to the analog input bandwidth limit. The internal voltage reference provides the gain accuracy required for calibrated measurement instruments where annual re-calibration cycles must hold drift within specification. The 28-SSOP/QSOP footprint simplifies board layout for modular instruments built from standardized digitizer mezzanine cards. In spectrum analyzer IF sections the part captures pre-filtered 21.4 MHz or 70 MHz IF signals aligned to the 60 MSPS Nyquist boundary.
Recomendado
Portable Battery-Powered Data Acquisition
Field-deployable data acquisition (DAQ) loggers and handheld spectrum analyzers benefit from the HI5767/4CA's low CMOS power dissipation and integrated voltage reference, both of which extend battery runtime and shrink the power supply to a single +5V rail. Selectable 20/40/60 MSPS modes let the firmware dynamically trade sample rate against power budget based on the user-selected bandwidth setting. Used in geological field surveys, vibration monitoring, and portable RF survey equipment where 10-bit SNR is acceptable at moderate sampling rates.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para HI5767/4CA — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | HI5766KCAZ | HI5767/6CA | HI5767/8CA | ADS901E | ADS901E/1K |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics (formerly Intersil) | Renesas Electronics (formerly Intersil) | Renesas Electronics (formerly Intersil) | Renesas Electronics (formerly Intersil) | Texas Instruments | Texas Instruments |
| Package | 28-SSOP/QSOP (PDSO28) | SSOP-28 | SSOP-28 | SSOP-28 | SSOP-28 | SSOP-28 |
| Resolution | 10 bits | 8 bits | 10 bits | 10 bits | 10 bits | 10 bits |
| Maximum Sampling Rate | 60 MSPS | 60 MSPS | 60 MSPS | 60 MSPS | 60 MSPS | 60 MSPS |
| Architecture | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS |
| Voltage Reference | Internal | Internal | Internal | Internal | External | External |
| Number of Input Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Lifecycle Status | NRND (sustained via Rochester Electronics) | NRND | NRND | NRND | Obsolete (TI) | Obsolete (TI) |
| Pin Count | 28 | 28 | 28 | 28 | 28 | 28 |
Principais diferenciais
- Internal bandgap voltage reference integrated (vs TI ADS901E (external reference required))
- 10-bit resolution upgrade path on same pinout (vs HI5766KCAZ (8-bit variant))
- Family-internal pin compatibility across speed grades (vs HI5767/6CA and HI5767/8CA)
Notas de projeto
Per the Intersil datasheet, separate the analog and digital ground planes with a single connection point at the AGND/DGND pins of the HI5767/4CA. Route analog input traces as 50-ohm controlled-impedance lines from the front-panel BNC connector. Place 0.1 uF ceramic decoupling capacitors adjacent to each AVDD and DVDD pin, with a 10 uF bulk tantalum at the IC supply entry point. This layout minimizes the digital switching noise floor at the analog input, preserving the part's stated SNR and SFDR performance.
Drive the CLK input of the HI5767/4CA with a low-jitter clock source (jitter below 5 ps RMS) for full 10-bit performance at 60 MSPS. Use a dedicated clock buffer (e.g., CDCV304) if the clock must be distributed to multiple ADCs or to a timing FPGA. Source-terminate the clock trace to suppress reflections on long clock-distribution paths. Clock jitter above 10 ps RMS will degrade SNR by 1-2 dB and is the most common cause of unexpected SNR shortfall in production boards.
The HI5767/4CA requires separate analog (AVDD) and digital (DVDD) supply rails, typically both +5V per the Intersil datasheet. Use a ferrite bead between the analog and digital supply rails and place bulk capacitance on each side. Estimated: power dissipation at 60 MSPS is approximately 200-300 mW based on the CMOS process and 10-bit pipelined architecture - confirm against datasheet figure before thermal budgeting. Add a 100 nF decoupling cap within 5 mm of each supply pin to suppress switching transients at full sampling rate.
Do not leave the OE (output enable) pin floating - tie it either to logic low or to DGND per the datasheet to put outputs in high-impedance state during power ramp-up. Avoid routing digital output busses (DB0-DB9) parallel to analog input traces - cross at 90 degrees and provide ground isolation between them. The internal bandgap voltage reference must be bypassed with a 10 uF + 0.1 uF capacitor at the VREF pin if used; otherwise the reference noise will couple into the sampling capacitor and degrade SNR by 3-5 dB.
Informações de conformidade
Compliance status of the HI5767/4CA original 28-SSOP/QSOP version is not explicitly stated in the verified web data. HI5767/4CA-Z variant is documented as lead-free per Renesas product family markings. Refer to the manufacturer datasheet marking column for the specific orderable suffix you receive.
