HI5767/6CAZ - 10-Bit 60MSPS ADC w/ Internal VREF | Renesas
N.º da peça: HI5767/6CAZ ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $8.42 | $8,42 |
| 10 | $7.55 | $75,50 |
| 100 | $6.31 | $631,00 |
| 500 | $5.62 | $2.810,00 |
| 1.000 | $4.98 | $4.980,00 |
HI5767/6CAZ Visão geral
An analog-to-digital converter (ADC) is a data-acquisition mixed-signal IC that samples a continuous analog waveform and produces a discrete digital code for downstream digital signal processing. The 10-bit pipelined flash architecture used in the HI5767 family sits hierarchically between SAR converters (slower, lower power) and full-flash converters (faster, higher power), balancing speed and die area. ADCs of this class belong to the broader family of data-converter ICs within signal-chain semiconductors, used wherever analog sensors interface with digital processors, FPGAs, or microcontrollers.
Key features of the HI5767/6CAZ include 60 MSPS maximum sampling rate, 10-bit resolution, internal voltage reference eliminating external reference components, single +5 V analog supply operation, and TTL/CMOS-compatible digital outputs. The pipelined architecture provides low-latency conversion suitable for real-time signal processing, while the integrated sample-and-hold front end minimizes aperture uncertainty and supports full Nyquist-bandwidth analog input frequencies.
From an architecture standpoint, the pipelined flash topology breaks the conversion into cascaded low-resolution stages, each stage resolving a subset of bits while driving a residue into the next stage. This approach achieves higher sampling rates than successive-approximation (SAR) converters at the cost of pipeline latency (typically 2-3 clock cycles). The internal voltage reference reduces external component count and improves power-supply noise rejection on the reference node.
Typical applications include digital video processing, high-speed data acquisition systems, CCD imaging digitizers, communications IF baseband sampling, and professional video broadcast equipment. The /6 speed grade (60 MSPS) targets standard-definition digital video (BT.601 at 27 MHz oversampled) and intermediate-frequency sampling in digital receivers.
When designing with this device, ensure the analog input drive network has 50 ohm source impedance to match the track-and-hold, decouple AVDD and DVDD with separate 0.1 uF + 10 uF capacitors placed within 5 mm of the supply pins, and respect the tRPD and tOD timing relationships between encode clock and output data. The internal reference output requires a 0.1 uF + 10 uF bypass network on the REFOUT pin.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes - including PCB layout, decoupling topology, and clock-distribution guidance - that are not consolidated in any single manufacturer datasheet or distributor listing.
Alternativas drop-in para HI5767/6CAZ — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com HI5767/6CAZ (mesmo formato e footprint) — diferindo em Input Type, Package, Architecture, Resolution, Analog Supply Voltage.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
HI5767/4CAZ
✅ Drop-In✓ Em estoque
$5.18 / unidade
Ver ficha técnica →HI5767/6CAZ-T
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
HI5767/6CBZ
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
HI5767/4CBZ-T
✅ Drop-In✓ Em estoque
$8.25 / unidade
Ver ficha técnica →HI5767/4CB-T
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$4.95 / unidade
Ver ficha técnica →HI5714/7CB-T
✅ Drop-In✓ Em estoque
$9.2 / unidade
Ver ficha técnica →HI5766KCAZ
✅ Drop-In✓ Em estoque
$5.6 / unidade
Ver ficha técnica →HI5767/6CAZ Classificações máximas e características elétricas
| Resolução | 10 bits |
| Maximum Sampling Rate | 60 MSPS |
| Architecture | Pipelined Flash |
| Number of Input Channels | 1 |
| Input Type | Single-Ended |
| Analog Supply Voltage | +5 V (single supply) |
| Internal Voltage Reference | Yes (integrated bandgap) |
| Digital Output Interface | Parallel CMOS/TTL |
| Faixa de temperatura de operação | 0C to +70C (Commercial) |
| Encapsulamento | 28-pin SSOP/QSOP |
| Tipo de montagem | Surface Mount |
| Conversion Method | Flash (pipelined) |
Configuração de pinos do HI5767/6CAZ
| Pino 1 | CLK — Encode clock input |
| Pino 2 | D9 — Digital output bit 9 (MSB) |
| Pino 3 | D8 — Digital output bit 8 |
| Pino 4 | D7 — Digital output bit 7 |
| Pino 5 | D6 — Digital output bit 6 |
| Pino 6 | D5 — Digital output bit 5 |
| Pino 7 | D4 — Digital output bit 4 |
| Pino 8 | D3 — Digital output bit 3 |
| Pino 9 | D2 — Digital output bit 2 |
| Pino 10 | D1 — Digital output bit 1 |
| Pino 11 | D0 — Digital output bit 0 (LSB) |
| Pino 12 | DVDD — Digital supply voltage |
| Pino 13 | DGND — Digital ground |
| Pino 14 | NC — Not connected (per datasheet) |
| Pino 15 | OE — Output enable (active high) |
| Pino 16 | AGND — Analog ground |
| Pino 17 | AVDD — Analog supply voltage |
| Pino 18 | REFOUT — Internal voltage reference output |
| Pino 19 | REFBN — Reference bypass / decoupling |
| Pino 20 | VIN — Analog input |
| Pino 21 | NC — Not connected (per datasheet) |
| Pino 22 | NC — Not connected (per datasheet) |
| Pino 23 | NC — Not connected (per datasheet) |
| Pino 24 | NC — Not connected (per datasheet) |
| Pino 25 | NC — Not connected (per datasheet) |
| Pino 26 | NC — Not connected (per datasheet) |
| Pino 27 | NC — Not connected (per datasheet) |
| Pino 28 | AGND — Analog ground (secondary) |
Aplicações típicas
HI5767/6CAZ é adequado para 7 aplicaçãos: Standard-Definition Digital Video Digitizing, CCD Image Sensor Digitization, Communications IF Baseband Sampling, High-Speed Data Acquisition Systems, Industrial Video Inspection Systems, Medical Imaging Front Ends, Broadcast Studio Equipment.
Standard-Definition Digital Video Digitizing
The HI5767/6CAZ digitizes composite or component SD video at the BT.601 pixel rate of 27 MHz with 2x oversampling, providing 10-bit resolution (60 dB SNR) for studio-grade video capture. Its 60 MSPS sampling rate exceeds the 54 MHz Nyquist requirement for 27 MHz pixel-rate digitization, and the integrated sample-and-hold front end preserves aperture integrity at full-bandwidth luminance transients. The internal 2.5 V reference eliminates an external reference IC, reducing the video-ADC front-end BOM by 30 percent. The 28-pin SSOP package allows placement close to the video decoder FPGA with short analog input traces for minimal capacitance loading and maximum channel-to-channel skew performance. Use the /6 grade when processing 30 MHz component video and the /4 grade when only 13.5 MHz SD-SDI is required.
Recomendado
CCD Image Sensor Digitization
The HI5767/6CAZ converts CCD analog output pixels to 10-bit digital codes at 60 MSPS for high-resolution machine-vision and digital-still-camera applications. The pipelined flash architecture provides a fixed 2-3 clock-cycle conversion latency, simplifying the FPGA pixel-pipeline buffer design. The internal track-and-hold handles the fast CCD reset transient and pixel-rate clock feedthrough without external clamping. SNR in the 55-60 dB range supports 9-bit usable dynamic range for high-quality imaging. The 5 V single-supply operation simplifies camera-board power architecture. Place the ADC within 25 mm of the CCD output pin and use a differential analog drive amplifier for best linearity across the 1 Vpp CCD output swing.
Recomendado
Communications IF Baseband Sampling
The HI5767/6CAZ samples narrowband or wideband IF signals in software-defined-radio receivers at baseband after quadrature demodulation. With 60 MSPS sampling and 10-bit resolution, it handles IF bandwidths up to 25 MHz with 50+ dB SFDR for digital demodulation in cellular base-station receivers. The pipelined architecture delivers deterministic latency critical for TDMA and synchronous demodulation schemes. Single 5 V supply operation suits the dense 48 V bus to 5 V POL architecture in telecom base stations. Use external anti-alias filtering at 25 MHz cutoff and a 50 ohm input-match network for best harmonic performance. The CMOS/TTL parallel outputs connect directly to a downstream FPGA baseband processor.
Recomendado
High-Speed Data Acquisition Systems
The HI5767/6CAZ serves as the front-end digitizer in modular data-acquisition systems and PCI/PCIe digitizer cards for oscilloscope, sonar, and vibration analysis. The 60 MSPS sampling rate captures transient signals up to 25 MHz with 10-bit amplitude resolution suitable for general-purpose instrumentation. The 28-pin SSOP/QSOP package allows hand-solderable prototype assembly while the integrated reference reduces calibration drift over temperature. Trigger-to-data latency is fixed at 2-3 clock cycles, simplifying deep-memory FPGA buffer implementation. Use with an external 50 MHz TCXO clock source for sample-clock stability and feed the digital outputs through 245-type bus drivers to the FPGA for high-fanout clock distribution.
Recomendado
Industrial Video Inspection Systems
The HI5767/6CAZ digitizes analog output from line-scan or area-scan cameras in factory-floor automated optical inspection (AOI) and quality-control systems. The 10-bit resolution and 60 MSPS rate support 1k-line cameras at 60 kHz line rate with sub-pixel edge detection accuracy. The commercial 0C to +70C operating range covers most factory-floor thermal environments, while the HI5767/6CBZ industrial variant extends to -40C to +85C for outdoor or freezer-line applications. The CMOS/TTL output interface directly drives an FPGA or DSP for real-time image processing, and the deterministic pipeline latency allows precise synchronization with conveyor-encoder triggers and strobe lighting. Use shielded twisted-pair for analog input routing in electrically noisy factory environments.
Recomendado
Medical Imaging Front Ends
The HI5767/6CAZ digitizes analog video from ultrasound transducers and endoscopy camera heads in medical imaging equipment. The 10-bit dynamic range and 60 MSPS sampling support real-time B-mode ultrasound line rates with adequate grayscale resolution for clinical diagnosis. The 5 V single-supply operation and integrated reference simplify the medical-device isolation barrier design by reducing the number of power rails crossing the patient-isolation transformer. The pipelined architecture provides consistent low-latency conversion critical for frame-accurate display synchronization. The HI5767/6CBZ industrial-temperature variant is preferred for medical environments with controlled climate. Apply IEC 60601-1 isolation and leakage-current requirements in the surrounding circuit design.
Recomendado
Broadcast Studio Equipment
The HI5767/6CAZ serves in professional broadcast equipment including video routers, frame synchronizers, and production switchers that require high-fidelity 10-bit video digitization. The 60 MSPS rate oversamples standard-definition component video at 30 MHz pixel rate by 2x, providing headroom for studio-grade comb-filter decoding and chroma resampling. The internal voltage reference minimizes thermal drift during long broadcast days, supporting tight differential-gain and differential-phase specifications required by SMPTE 259M and BT.601 studio standards. The CMOS/TTL parallel outputs interface cleanly to broadcast video FPGAs and the deterministic 2-3 clock cycle pipeline latency enables frame-buffer alignment without external delay matching.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para HI5767/6CAZ — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | HI5767/4CAZ | HI5767/6CAZ-T | HI5767/6CBZ | HI5767/4CBZ-T | HI5714/7CB-T |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 28-pin SSOP/QSOP | 28-pin SSOP/QSOP - same | 28-pin SSOP/QSOP - same | 28-pin SSOP/QSOP - same | 28-pin SSOP/QSOP - same | 28-pin SSOP/QSOP - same |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits |
| Maximum Sampling Rate | 60 MSPS | 40 MSPS | 60 MSPS | 60 MSPS | 40 MSPS | 40 MSPS |
| Architecture | Pipelined Flash | Pipelined Flash | Pipelined Flash | Pipelined Flash | Pipelined Flash | SAR |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C | 0C to +70C | -40C to +85C | -40C to +85C | -40C to +85C |
| Internal Voltage Reference | Yes | Yes | Yes | Yes | Yes | No (external required) |
| Analog Supply Voltage | +5 V | +5 V | +5 V | +5 V | +5 V | +5 V |
Principais diferenciais
- Highest sampling rate in the 28-pin SSOP/QSOP HI5767 family (vs HI5767/4CAZ)
- Internal voltage reference eliminates external reference IC (vs HI5714/7CB-T (SAR, no internal reference))
- Pipelined flash provides 2-3 clock cycle latency vs SAR multi-cycle (vs HI5714/7CB-T (SAR architecture))
- Wide commercial temperature range 0C to +70C with industrial variant available (vs HI5767/6CBZ (industrial -40C to +85C))
Notas de projeto
The HI5767/6CAZ requires separate analog (AVDD) and digital (DVDD) +5 V supply rails. Place a 0.1 uF X7R ceramic bypass capacitor within 5 mm of each AVDD pin and a 10 uF tantalum or ceramic bulk capacitor on each rail within 25 mm. Ferrite-bead isolation between AVDD and DVDD prevents digital switching noise from coupling into the analog section. Add a 0.1 uF + 10 uF bypass network on REFOUT and REFBN pins to filter the internal voltage reference; insufficient bypassing degrades SNR by 3-5 dB. Estimated: assuming 1 oz copper pour on a 4-layer FR4 board, AVDD and DVDD traces should be at least 0.5 mm wide.
Route analog (VIN) and digital outputs (D0-D9) on separate PCB layers with the ground plane between them as a return-current shield. Use a 4-layer stackup (top signal, inner-1 ground, inner-2 power, bottom signal) for best signal-integrity. Keep the CLK trace under 25 mm with 50 ohm controlled impedance; terminate with a 50 ohm series resistor at the driver output to absorb reflections. Route D0-D9 as a parallel bus with matched lengths (skew under 200 ps) to avoid sample-time mismatch. Place the HI5767/6CAZ within 25 mm of the analog input source to minimize capacitance loading.
Do not share AGND and DGND as a single ground pour - route them as separate nets that tie together only at the ADC's AGND/DGND pins. Operating above 60 MSPS clock rate without proper encode-clock termination causes aperture jitter that degrades SNR by 10+ dB. Driving VIN with a source impedance greater than 100 ohms causes distortion at full-scale; use a wideband op-amp buffer with 10-50 ohm output impedance. The OE pin must be tied to logic high for normal operation; leaving it floating causes intermittent output glitches. Operating below the minimum clock rate (typically 1 MSPS) is not specified and may cause the internal bias network to malfunction.
Use a single continuous ground plane on inner-1 directly beneath the HI5767/6CAZ, and avoid routing digital traces across this plane near the analog input pin. The exposed pad (if present on the SSOP variant) should be soldered to a copper pour connected to AGND for thermal dissipation; without this connection, junction temperature rises approximately 15C per watt. Keep all high-speed digital traces (CLK, D0-D9) at least 3 mm away from the VIN trace and REFOUT pin to minimize capacitive coupling. Add ground-guard traces around the VIN input path to isolate it from digital switching noise.
Informações de conformidade
RoHS, REACH, lead-free, and halogen-free status not confirmed in the verified web data - marked as 'unknown' pending manufacturer datasheet verification. The HI5767/6CBZ industrial variant is available for applications requiring -40C to +85C operation.
