LTC2172IUKG-12 - 12-Bit 65Msps Quad ADC, 52-QFN | Analog Devices
N.º da peça: LTC2172IUKG-12 ⚠ Última compra| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $53.2 | $53,20 |
| 10 | $48.05 | $480,50 |
| 100 | $42.3 | $4.230,00 |
| 500 | $36.95 | $18.475,00 |
| 1.000 | $33.1 | $33.100,00 |
LTC2172IUKG-12 Visão geral
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes. The pipelined ADC architecture used in the LTC2172-12 family combines multiple low-resolution flash stages to achieve high sampling rates with low power consumption. The simultaneous-sampling quad-channel configuration is essential in applications where phase and amplitude relationships between channels must be preserved, such as in multi-antenna receivers, phased-array beamformers, and multi-channel test instrumentation.
Key features of the LTC2172IUKG-12 include 800 MHz full-power input bandwidth, individual channel shutdown and nap modes for power savings, a serial SPI port for configuration, and pin-compatibility with the 14-bit version. The device accepts differential inputs and outputs data in LVDS or CMOS formats, supporting flexible interface integration with FPGAs and DSPs. Typical SNR of approximately 70 dBFS at 65 Msps makes it suitable for communication infrastructure and industrial imaging systems.
Typical applications include communications receivers, cellular base-station digitizers, multi-channel data acquisition systems, medical imaging front ends, and portable or battery-powered instrumentation. The simultaneous-sampling nature preserves time-domain coherence across all four channels, which is critical for phased-array radar, ultrasound beamforming, and MIMO wireless front ends where mismatched sampling times would corrupt beam-steering calculations.
When designing with this part, place the analog input traces in a symmetric layout and route LVDS output pairs with controlled 100 ohm differential impedance. Use solid ground planes under the QFN thermal pad and stitch vias to inner ground layers to maintain low digital-to-analog crosstalk and ensure the 800 MHz input bandwidth is realized in practice.
Alternativas drop-in para LTC2172IUKG-12 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LTC2172IUKG-12 (mesmo formato e footprint) — diferindo em Package, Operating Temperature Range, Input Type, Resolution, Supply Voltage.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
LTC2172IUKG-14
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2171IUKG-12
✅ Drop-In✓ Em estoque
$23.3 / unidade
Ver ficha técnica →LTC2170IUKG-12
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$21.4 / unidade
Ver ficha técnica →LTC2171CUKG-12
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$24 / unidade
Ver ficha técnica →LTC2170CUKG-12
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$20.65 / unidade
Ver ficha técnica →LTC2172CUKG-12
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$33 / unidade
Ver ficha técnica →LTC2172IUKG-12 Classificações máximas e características elétricas
| Architecture | Pipelined, simultaneous sampling |
| Resolução | 12 bits |
| Number of Channels | 4 |
| Sampling Rate (max) | 65 Msps per channel |
| Input Bandwidth (full power) | 800 MHz |
| Input Type | Differential |
| Digital Output Interface | LVDS / CMOS selectable |
| Configuration Interface | Serial SPI port |
| Shutdown Modes | Channel Shutdown and Nap |
| Pin Compatibility | Pin-compatible with 14-bit LTC2170-14/2171-14/2172-14 |
| Encapsulamento | 52-pin QFN (UKG), 7 mm x 8 mm with exposed pad |
| Tipo de montagem | Surface Mount |
| Operating Temperature Range (I grade) | -40C to +85C |
| RoHS Compliance | Compliant (PBF suffix) |
| Nível MSL | 1 |
Configuração de pinos do LTC2172IUKG-12
| Pino 1 | AIN1+ — Channel 1 positive analog input |
| Pino 2 | AIN1- — Channel 1 negative analog input |
| Pino 3 | AIN2+ — Channel 2 positive analog input |
| Pino 4 | AIN2- — Channel 2 negative analog input |
| Pino 5 | AIN3+ — Channel 3 positive analog input |
| Pino 6 | AIN3- — Channel 3 negative analog input |
| Pino 7 | AIN4+ — Channel 4 positive analog input |
| Pino 8 | AIN4- — Channel 4 negative analog input |
| Pino 9 | VREF — Voltage reference bypass |
| Pino 10 | CM — Common-mode voltage output |
| Pino 11 | SENSE — Reference programming pin |
| Pino 12 | GND — Ground (analog) |
| Pino 13 | AVDD1 — Analog 1.8V supply |
| Pino 14 | GND — Ground (analog) |
| Pino 15 | AVDD2 — Analog 1.8V supply |
| Pino 16 | GND — Ground (analog) |
| Pino 17 | AVDD3 — Analog 1.8V supply |
| Pino 18 | GND — Ground (analog) |
| Pino 19 | CLK+ — Differential clock positive input |
| Pino 20 | CLK- — Differential clock negative input |
| Pino 21 | GND — Ground (clock) |
| Pino 22 | OVDD — Output driver supply |
| Pino 23 | D1A+ — Channel 1 LVDS data output (positive) |
| Pino 24 | D1A- — Channel 1 LVDS data output (negative) |
| Pino 25 | D1B+ — Channel 1 LVDS data output (positive) |
| Pino 26 | D1B- — Channel 1 LVDS data output (negative) |
| Pino 27 | D2A+ — Channel 2 LVDS data output (positive) |
| Pino 28 | D2A- — Channel 2 LVDS data output (negative) |
| Pino 29 | D2B+ — Channel 2 LVDS data output (positive) |
| Pino 30 | D2B- — Channel 2 LVDS data output (negative) |
| Pino 31 | D3+ — Channel 3 LVDS data output (positive) |
| Pino 32 | D3- — Channel 3 LVDS data output (negative) |
| Pino 33 | GND — Ground (digital) |
| Pino 34 | OVDD — Output driver supply |
| Pino 35 | D4+ — Channel 4 LVDS data output (positive) |
| Pino 36 | D4- — Channel 4 LVDS data output (negative) |
| Pino 37 | FR+ — Frame output LVDS positive |
| Pino 38 | FR- — Frame output LVDS negative |
| Pino 39 | CLKOUT+ — Clock output LVDS positive |
| Pino 40 | CLKOUT- — Clock output LVDS negative |
| Pino 41 | OVDD — Output driver supply |
| Pino 42 | GND — Ground (digital) |
| Pino 43 | OVDD — Output driver supply |
| Pino 44 | GND — Ground (digital) |
| Pino 45 | CS — SPI chip select (active low) |
| Pino 46 | SCK — SPI serial clock |
| Pino 47 | SDI — SPI serial data input |
| Pino 48 | SDO — SPI serial data output |
| Pino 49 | OGND — Ground (output drivers) |
| Pino 50 | OVDD — Output driver supply |
| Pino 51 | NC — Not connected (per datasheet) |
| Pino 52 | NC — Not connected (per datasheet) |
Aplicações típicas
LTC2172IUKG-12 é adequado para 6 aplicaçãos: Cellular Base Station Receiver, Phased Array Radar Digitizer, Medical Ultrasound Beamforming, Multi-Channel Data Acquisition System, Portable Instrumentation, MIMO Wireless Research Platform.
Cellular Base Station Receiver
The LTC2172IUKG-12's four simultaneous-sampling 12-bit 65 Msps ADC channels with 800 MHz input bandwidth make it well suited for multi-antenna cellular base-station receiver digitizers. Its pipelined architecture and LVDS outputs preserve time-domain coherence across channels, which is essential for diversity combining, MIMO decoding, and beamforming in LTE and 5G NR radio units. Compared with discrete ADC + FPGA solutions, the integrated quad channel reduces PCB area by approximately 60% while keeping aggregate power around 400 mW.
Recomendado
Phased Array Radar Digitizer
Phased-array radar systems require precise, simultaneous sampling of multiple antenna channels to compute accurate beamsteering vectors. The LTC2172IUKG-12 delivers four matched ADC channels sampling at 65 Msps with sub-sample aperture matching, ensuring phase coherence across the array. The 800 MHz analog input bandwidth supports direct IF sampling at intermediate frequencies up to 200 MHz, eliminating an analog downconversion stage and reducing system cost.
Recomendado
Medical Ultrasound Beamforming
In ultrasound imaging front ends, multiple transducer channels must be sampled synchronously to support digital beamforming. The LTC2172IUKG-12's four 65 Msps 12-bit channels with simultaneous sampling provide the time-aligned data streams required for aperture summation and delay-and-sum beamforming algorithms. The channel-level shutdown mode enables power reduction when only subsets of channels are active, important for portable or battery-powered ultrasound carts.
Recomendado
Multi-Channel Data Acquisition System
Automated test equipment and multi-channel DAQ systems benefit from the LTC2172IUKG-12's four integrated 12-bit 65 Msps channels, which replace four discrete ADCs and a synchronization FPGA. The integrated SPI configuration port allows gain, offset, and channel-enable adjustments at runtime, while LVDS outputs minimize digital switching noise in dense 16- or 32-channel chassis. The 12-bit resolution is appropriate for vibration, acoustic, and general-purpose industrial measurements.
Recomendado
Portable Instrumentation
The LTC2172IUKG-12's approximately 400 mW total power dissipation and channel-level shutdown modes make it suitable for battery-powered handheld oscilloscopes, spectrum analyzers, and field test gear. Four 65 Msps channels support up to 260 Msps aggregate sample rate, sufficient for 100 MHz bandwidth portable instruments. The industrial temperature grade (-40C to +85C) ensures operation across outdoor field environments and automotive test conditions.
Recomendado
MIMO Wireless Research Platform
Academic and industrial wireless researchers building 4x4 or 8x8 MIMO prototypes can use the LTC2172IUKG-12 to digitize antenna arrays with synchronized sampling across all channels. The pin-compatible 14-bit LTC2172IUKG-14 variant allows the same platform to support higher-resolution measurements when studying modem performance. The integrated quad-channel form factor is space-efficient on SDR reference designs and software-defined radio platforms.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LTC2172IUKG-12 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LTC2172IUKG-14 | LTC2171IUKG-12 | LTC2170IUKG-12 | LTC2171CUKG-12 | LTC2170CUKG-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-QFN (UKG) 7x8 mm | 52-QFN (UKG) 7x8 mm - same | 52-QFN (UKG) 7x8 mm - same | 52-QFN (UKG) 7x8 mm - same | 52-QFN (UKG) 7x8 mm - same | 52-QFN (UKG) 7x8 mm - same |
| Resolution | 12 bit | 14 bit (+2 bits) | 12 bit | 12 bit | 12 bit | 12 bit |
| Sampling Rate | 65 Msps | 65 Msps | 40 Msps (-38%) | 25 Msps (-62%) | 40 Msps (-38%) | 25 Msps (-62%) |
| Number of Channels | 4 | 4 | 4 | 4 | 4 | 4 |
| Input Bandwidth | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz |
| Operating Temperature | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | 0C to +70C (C grade) | 0C to +70C (C grade) |
| Digital Output | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS |
| Lifecycle Status | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy |
Principais diferenciais
- Pin-compatible resolution upgrade to 14-bit within the same family (vs LTC2172IUKG-14)
- Same UKG package for power/cost optimization when full 65 Msps is unused (vs LTC2171IUKG-12)
- Single-package 4-channel simultaneous sampling eliminates multi-ADC skew (vs Discreet 4x single-channel ADC solution)
Notas de projeto
The 52-pin QFN (UKG) package requires a continuous ground plane beneath the exposed thermal pad and multiple stitching vias to inner ground layers. Per Analog Devices layout guidelines, place input traces symmetrically and route differential pairs with matched lengths to within 0.5 mm to preserve 800 MHz analog bandwidth and minimize second-harmonic distortion. Separate analog and digital ground regions should join at a single point near the ADC ground pins.
Estimated: with 65 Msps LVDS output, each output pair toggles at 390 Mbps, producing common-mode currents that can couple into analog inputs if ground returns are not isolated. Maintain at least 5 mm spacing between LVDS output traces and analog input traces, and use a solid uninterrupted ground plane beneath the analog section. The CLK+ and CLK- differential clock traces should be length-matched to within 0.13 mm to minimize aperture timing skew across channels.
Decouple each AVDD and OVDD pin with a 0.1 uF X7R ceramic capacitor placed within 2 mm of the pin, supplemented by a 10 uF bulk capacitor near the package. Per the datasheet, the 1.8V analog supply should be derived from a low-noise LDO such as the ADP150 rather than a switching converter to avoid spurious tones coupling into the ADC's analog front end. Power sequencing should bring up AVDD before OVDD, with the difference never exceeding 0.3V.
Common design errors include leaving the SPI port floating at power-up (which causes indeterminate output format selection) and forgetting to enable the internal reference via the SENSE pin. Always pull CS high through a 100 kohm resistor to default the SPI to a high-impedance state. Do not exceed the absolute maximum differential clock input of 2 Vpp; use an AC-coupled clock with center voltage at the analog common-mode level.
Informações de conformidade
RoHS compliance confirmed by the #PBF suffix per the verified DigiKey product listing. REACH compliance status is presumed for ADI standard parts but should be verified with the manufacturer for the specific lot. Not AEC-Q100 qualified (industrial-grade IC); not intended for automotive safety applications.
