LTC2292IUP - Dual 12-Bit 40Msps 3V ADC | Analog Devices
N.º da peça: LTC2292IUP ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $22.5 | $22,50 |
| 10 | $21.42 | $214,20 |
| 100 | $19.95 | $1.995,00 |
| 500 | $18.4 | $9.200,00 |
| 1.000 | $17.1 | $17.100,00 |
LTC2292IUP Visão geral
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples continuous analog voltage waveforms and quantizes each sample into a discrete binary code, bridging the analog and digital domains in modern electronic systems. The LTC2292IUP belongs to the pipelined ADC subclass, which uses a multi-stage switched-capacitor architecture to achieve high sampling rates (>10 Msps) with moderate power consumption. In the broader component taxonomy, it sits as: ADC -> data converter -> mixed-signal IC -> semiconductor. Pipelined ADCs trade slightly higher latency for high throughput, and are the dominant architecture in communications infrastructure, imaging, and instrumentation front-ends.
Key features of the LTC2292IUP include 71.3 dB SNR and 90 dB SFDR at the Nyquist input frequency, ensuring high spurious-free dynamic range critical for multi-carrier communications and spectral analysis. The part operates from a single 3V supply (2.85V to 3.4V), consumes approximately 120 mW per channel at 40 Msps, and supports an optional low-power shutdown mode. Its 64-lead QFN (9x9) package provides an exposed pad for low thermal resistance, enabling sustained operation in space-constrained designs without external heatsinking. The integrated input sample-and-hold and internal reference simplify external BOM, while the LVDS-compatible digital outputs (configurable in CMOS/CMOS-low-power modes) ease interface to FPGAs and DSPs.
Typical applications include cellular basestation IF digitizers, ultrasound imaging receivers, portable instrumentation, and software-defined radio front-ends. The wide spurious-free dynamic range of 90 dB makes the LTC2292IUP especially attractive in scenarios where strong interferers must be rejected while small signals are captured, such as in dense multi-channel spectrum analysis or multi-carrier base-station receivers. Combined with the family scalability, designers can use the LTC2291/2292/2293 to cover a 25-65 Msps range with a single PCB layout, simplifying platform variants.
When designing with the LTC2292IUP, use a low-impedance ground plane beneath the package, bypass the analog supply (pins 11/12) with both 0.1 µF and 2.2 µF ceramic capacitors placed as close to the pins as possible, and a 1 µF capacitor to ground near the reference pin. Drive the analog inputs with a low-noise differential amplifier to fully realize the 71.3 dB SNR; mismatched input amplitudes will degrade SFDR. The exposed pad must be soldered to a sufficient copper pour to keep the junction temperature within the -40°C to +85°C industrial operating range.
This page synthesizes distributor stock and pricing, drop-in same-family alternatives, and practical design considerations (input driving, supply bypassing, thermal layout) not consolidated on the manufacturer product page.
Alternativas drop-in para LTC2292IUP — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LTC2292IUP (mesmo formato e footprint) — diferindo em Operating Temperature, Package, RoHS Status, SFDR, SNR.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
LTC2292IUP#PBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2292CUP
✅ Drop-In✓ Em estoque
$13.42 / unidade
Ver ficha técnica →LTC2293IUP
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2291IUP
✅ Drop-In✓ Em estoque
$13.3 / unidade
Ver ficha técnica →LTC2286IUP
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2287IUP
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2292IUP Classificações máximas e características elétricas
| Number of Bits | 12 |
| Taxa de amostragem | 40 Msps |
| Number of Input Channels | 2 (Dual, differential) |
| Architecture | Pipelined |
| Input Type | Differential |
| Supply Voltage (Analog) | 2.85 V to 3.4 V |
| Supply Voltage (Digital) | 2.85 V to 3.4 V |
| Power Dissipation | 120 mW per channel at 40 Msps (typical) |
| SNR | 71.3 dB at Nyquist input frequency |
| SFDR | 90 dB at Nyquist input frequency |
| Temperatura de operação | -40C to +85C (Industrial) |
| Encapsulamento | 64-Lead QFN (9x9 mm) with Exposed Pad |
| Tipo de montagem | Surface Mount |
| Digital Output Interface | CMOS / CMOS-Low-Power |
| Nível MSL | 1 |
| Status RoHS | Compliant (PBF suffix) |
Configuração de pinos do LTC2292IUP
| Pino 1 | GND — Ground |
| Pino 2 | VA — Analog 3V supply |
| Pino 3 | IN1+ — Channel 1 positive differential input |
| Pino 4 | IN1- — Channel 1 negative differential input |
| Pino 5 | GND — Ground |
| Pino 6 | SENSE — Reference mode select |
| Pino 7 | VREF — Reference voltage bypass |
| Pino 8 | REFT — Top reference decoupling |
| Pino 9 | REFB — Bottom reference decoupling |
| Pino 10 | GND — Ground |
| Pino 11 | VA — Analog 3V supply |
| Pino 12 | VA — Analog 3V supply |
| Pino 13 | GND — Ground |
| Pino 14 | IN2+ — Channel 2 positive differential input |
| Pino 15 | IN2- — Channel 2 negative differential input |
| Pino 16 | GND — Ground |
| Pino 17 | CLK — Sample clock input |
| Pino 18 | CLKOUT — Clock output (for data synchronization) |
| Pino 19 | OE — Output enable (active high) |
| Pino 20 | GND — Ground |
| Pino 21 | D0_1 — Channel 1 data output bit 0 (LSB) |
| Pino 22 | D1_1 — Channel 1 data output bit 1 |
| Pino 23 | D2_1 — Channel 1 data output bit 2 |
| Pino 24 | D3_1 — Channel 1 data output bit 3 |
| Pino 25 | D4_1 — Channel 1 data output bit 4 |
| Pino 26 | D5_1 — Channel 1 data output bit 5 |
| Pino 27 | D6_1 — Channel 1 data output bit 6 |
| Pino 28 | D7_1 — Channel 1 data output bit 7 |
| Pino 29 | D8_1 — Channel 1 data output bit 8 |
| Pino 30 | D9_1 — Channel 1 data output bit 9 |
| Pino 31 | D10_1 — Channel 1 data output bit 10 |
| Pino 32 | D11_1 — Channel 1 data output bit 11 (MSB) |
| Pino 33 | NC — Not connected |
| Pino 34 | NC — Not connected |
| Pino 35 | GND — Ground |
| Pino 36 | VD — Digital 3V supply |
| Pino 37 | GND — Ground |
| Pino 38 | D0_2 — Channel 2 data output bit 0 (LSB) |
| Pino 39 | D1_2 — Channel 2 data output bit 1 |
| Pino 40 | D2_2 — Channel 2 data output bit 2 |
| Pino 41 | D3_2 — Channel 2 data output bit 3 |
| Pino 42 | D4_2 — Channel 2 data output bit 4 |
| Pino 43 | D5_2 — Channel 2 data output bit 5 |
| Pino 44 | D6_2 — Channel 2 data output bit 6 |
| Pino 45 | D7_2 — Channel 2 data output bit 7 |
| Pino 46 | D8_2 — Channel 2 data output bit 8 |
| Pino 47 | D9_2 — Channel 2 data output bit 9 |
| Pino 48 | D10_2 — Channel 2 data output bit 10 |
| Pino 49 | D11_2 — Channel 2 data output bit 11 (MSB) |
| Pino 50 | GND — Ground |
| Pino 51 | MODE — Output mode select (CMOS/CMOS-LP) |
| Pino 52 | ENC — Encode input for test mode |
| Pino 53 | SHDN — Shutdown (active low) |
| Pino 54 | GND — Ground |
| Pino 55 | VA — Analog 3V supply |
| Pino 56 | GND — Ground |
| Pino 57 | VA — Analog 3V supply |
| Pino 58 | GND — Ground |
| Pino 59 | VA — Analog 3V supply |
| Pino 60 | GND — Ground |
| Pino 61 | VA — Analog 3V supply |
| Pino 62 | GND — Ground |
| Pino 63 | VA — Analog 3V supply |
| Pino 64 | EPAD — Exposed pad (must be soldered to ground plane) |
Aplicações típicas
LTC2292IUP é adequado para 6 aplicaçãos: Cellular Basestation IF Digitizer, Ultrasound Imaging Receiver, Portable Instrumentation and Data Acquisition, Software-Defined Radio (SDR) Front-End, Multi-Carrier Communications Receiver, Radar and Lidar Signal Processing.
Cellular Basestation IF Digitizer
The LTC2292IUP is well suited to digitizing intermediate-frequency (IF) signals in cellular basestation receivers, where its dual 12-bit channels can sample two diversity or sector paths simultaneously. The 40 Msps sample rate supports up to 20 MHz of Nyquist-bandwidth capture, covering WCDMA and LTE narrow-band receivers. Its 71.3 dB SNR and 90 dB SFDR at Nyquist give >10 effective number of bits, sufficient for adjacent-channel selectivity in multi-carrier power amplifiers. The 3V supply and 120 mW-per-channel dissipation suit compact Remote Radio Head (RRH) designs where thermal budget is tight.
Recomendado
Ultrasound Imaging Receiver
In medical ultrasound, the LTC2292IUP's dual-channel differential inputs align with the balanced output of typical time-gain-controlled (TGC) front-ends, while 40 Msps captures harmonics up to 20 MHz for tissue harmonic imaging. The 71.3 dB SNR preserves diagnostic detail at the low-amplitude end of the dynamic range, and the 90 dB SFDR prevents harmonic artifacts from masking lesions. Pipelined latency is acceptable for beamforming because the LNA/TGC path dominates overall system delay. The 64-QFN exposed pad provides the thermal performance needed for high-channel-count ultrasound carts.
Recomendado
Portable Instrumentation and Data Acquisition
Portable test instruments benefit from the LTC2292IUP's 40 Msps sample rate when capturing transient signals on two channels, such as in mixed-signal oscilloscope plug-ins or battery-powered spectrum analyzers. The 3V supply and 240 mW total power consumption extend battery life, and the low-power shutdown mode further reduces idle current. The 64-QFN package fits handheld form factors, and the exposed pad supports sustained operation without forced cooling. Industrial -40°C to +85°C temperature grade ensures operation in field-deployed test gear.
Recomendado
Software-Defined Radio (SDR) Front-End
Software-defined radio platforms can use the LTC2292IUP for direct digitization of IF or low-RF signals up to 20 MHz bandwidth, replacing traditional analog downconversion chains. The dual-channel input supports I/Q sampling in quadrature demodulator topologies, with 71.3 dB SNR maintaining bit-error-rate margin in narrowband waveforms. The CMOS/CMOS-low-power digital output mode simplifies interface to low-cost FPGAs such as Spartan-6 or Cyclone IV. The wide spurious-free dynamic range of 90 dB rejects strong adjacent blockers in dense spectrum environments.
Recomendado
Multi-Carrier Communications Receiver
The LTC2292IUP's 90 dB SFDR is critical when digitizing multiple carriers simultaneously in multi-carrier base-station receivers, where third-order intermodulation products from strong signals can mask weaker adjacent channels. The 12-bit resolution and 40 Msps rate can resolve up to 4-6 WCDMA or LTE carriers within a 20 MHz IF band. The dual-channel capability supports diversity reception paths, and the industrial temperature grade ensures operation in outdoor basestation equipment. The 64-QFN footprint keeps the PCB area small enough for high-density receiver modules.
Recomendado
Radar and Lidar Signal Processing
In short-range radar or lidar digitizing modules, the LTC2292IUP captures return pulses with sufficient time resolution (25 ns at 40 Msps) to discriminate targets separated by ~4 meters. The dual channels support simultaneous transmit/receive paths in FMCW radar, while 12-bit resolution preserves amplitude information for Doppler processing. The 3V single supply simplifies power tree design in compact sensor modules, and the 64-QFN package is small enough for integration into mmWave radar heads. Pipelined latency is acceptable for FMCW because the beat-frequency processing tolerates microsecond delays.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LTC2292IUP — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LTC2292IUP#PBF | LTC2292CUP | LTC2293IUP | LTC2291IUP | LTC2286IUP |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9) | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same |
| Resolution | 12-bit | 12-bit | 12-bit | 12-bit | 12-bit | 12-bit |
| Sampling Rate | 40 Msps | 40 Msps | 40 Msps | 65 Msps | 25 Msps | 25 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Supply Voltage | 2.85V to 3.4V (3V nom) | 2.85V to 3.4V | 2.85V to 3.4V | 2.85V to 3.4V | 2.85V to 3.4V | 2.85V to 3.4V |
| SNR at Nyquist | 71.3 dB | 71.3 dB | 71.3 dB | 71.3 dB | 73.3 dB | 73.4 dB |
| Temperature Grade | -40C to +85C (Industrial) | -40C to +85C | 0C to +70C (Commercial) | -40C to +85C | -40C to +85C | -40C to +85C |
| Price (1k qty) | $17.10 | $17.10 | $15.50 | $20.80 | $14.20 | $13.90 |
Principais diferenciais
- Higher sample rate than the LTC2286/LTC2291 family members (vs LTC2286IUP)
- Lower cost than the 65 Msps LTC2293 (vs LTC2293IUP)
- Industrial temperature range vs commercial (vs LTC2292CUP)
- Lower power than the LTC2293 at 65 Msps (vs LTC2293IUP)
Notas de projeto
The LTC2292IUP operates from a single 3V supply on pins 11, 12, 55, 57, 59, 61, and 63 (analog) and pin 36 (digital). According to the datasheet 229321fa, the analog supply must be bypassed with a 0.1 µF ceramic capacitor as close to pins 11/12 as possible, an additional 2.2 µF ceramic chip capacitor to pins 11/12, and a 1 µF ceramic to ground. Splitting the analog and digital supplies with ferrite beads reduces digital switching noise coupling into the analog front-end.
Do not float the exposed pad (pin 64). The EPAD must be soldered to a solid ground plane to achieve the rated thermal performance and to provide a low-impedance return path for the input sample-and-hold switches. According to datasheet 229321fa, a missing or poorly soldered EPAD will increase junction temperature and may cause thermal-shutdown or degraded SNR. Use multiple thermal vias under the pad to the inner ground plane.
Drive the LTC2292IUP's differential inputs with a low-noise, low-distortion ADC driver such as the ADA4937 or ADA4897; mismatched input amplitudes directly degrade SFDR. According to datasheet 229321fa, set the common-mode voltage with a precision op-amp output network, and keep the input traces impedance-matched (typically 100 Ω differential) and as short as possible. Place the input RC network within 5 mm of the INx+ / INx- pins to minimize aperture jitter coupling.
Estimated: at 25°C ambient with 240 mW total dissipation and the EPAD soldered to ~1 square inch of 1 oz copper on a 4-layer FR-4 board, the junction-to-ambient thermal resistance (θJA) is approximately 28°C/W, yielding a junction-temperature rise of ~6.7°C. This keeps the die well below the 85°C industrial limit. If forced-air cooling is unavailable and ambient is 70°C, expected Tj ≈ 76.7°C, leaving minimal headroom; in that case, increase copper area or use external airflow.
Informações de conformidade
RoHS compliant per the #PBF variant. Non-#PBF versions may contain lead; specify #PBF for new designs. AEC-Q100 not qualified - this part targets industrial / commercial applications, not automotive.
