LTC2321CUFD-12 - Dual 12-Bit+Sign 2Msps SAR ADC | ADI
N.º da peça: LTC2321CUFD-12 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $8.95 | $8,95 |
| 10 | $8.2 | $82,00 |
| 100 | $7.45 | $745,00 |
| 500 | $6.8 | $3.400,00 |
| 1.000 | $6.1 | $6.100,00 |
LTC2321CUFD-12 Visão geral
A successive-approximation-register (SAR) ADC is a precision converter architecture that performs a binary search on the analog input each conversion cycle, converting in a single clock step per bit (N+1 clocks for an N-bit result). Compared with sigma-delta and pipeline architectures, SAR converters offer deterministic latency, excellent DC linearity, low power consumption, and no pipeline delay, which makes them the preferred topology for multiplexed data acquisition, control loops, and multi-phase power monitoring where time-domain accuracy matters as much as raw sample rate.
The LTC2321-12 family integrates a precision internal reference and reference buffer, two high-bandwidth differential track-and-hold front ends, and a flexible CMOS/ LVDS-compatible serial LVDS interface. The differential inputs accept rail-to-rail common-mode swings, allowing the ADC to digitize signals riding on a wide range of DC bias points. An external reference option is also supported. The wide common-mode range eliminates the need for level-shifting op-amps ahead of the ADC in many industrial and instrumentation designs.
Designed for low noise and high dynamic performance, the LTC2321CUFD-12 targets demanding applications such as industrial process control, multi-phase motor current sensing, high-speed data acquisition systems, medical imaging front ends, and ATE (automatic test equipment) signal capture. The dual simultaneous-sampling channels are particularly valuable in three-phase power monitoring, where two phase currents must be sampled at the exact same instant to compute instantaneous power without phase-skew error.
When designing with this ADC, place the analog input RC network as close as possible to the IN+ / IN- pins to minimize charge kickback, and follow the manufacturer's recommended reference decoupling scheme. Use a low-jitter LVDS clock source for the conversion clock to avoid degrading SNR. The internal reference settles in a few milliseconds after power-up - allow adequate wake-up time before triggering conversions.
Alternativas drop-in para LTC2321CUFD-12 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LTC2321CUFD-12 (mesmo formato e footprint) — diferindo em Internal Reference, Number of Channels, Package, Resolution, Differential Input Range.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
LTC2321IUFD-12
✅ Drop-In✓ Em estoque
$9.66 / unidade
Ver ficha técnica →LTC2321HUFD-12
✅ Drop-In✓ Em estoque
$5.62 / unidade
Ver ficha técnica →LTC2321CUFD-12#PBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2321CUFD-12#TRPBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2323CUFD-12
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2321CUFD-12 Classificações máximas e características elétricas
| Resolução | 12 bits + sign |
| Number of Channels | 2 (simultaneous sampling) |
| Sampling Rate (per channel) | 2 Msps |
| Architecture | SAR (Successive Approximation Register) |
| Input Type | Differential |
| Differential Input Range | 8 Vp-p |
| Tensão de alimentação | 3.3 V or 5 V single supply |
| Input Common-Mode Range | Wide (rail-to-rail capable) |
| Internal Reference | Yes (precision, with buffer) |
| Digital Interface | Serial LVDS / CMOS compatible |
| Encapsulamento | 28-pin QFN (4 mm x 5 mm) |
| Temperatura de operação | 0C to +70C (C grade) |
| Status RoHS | Compliant |
| Lead-Free | Yes (PBF suffix) |
| AEC-Q100 Qualified | No |
Configuração de pinos do LTC2321CUFD-12
| Pino 1 | GND — Ground |
| Pino 2 | IN1+ — Channel 1 differential input, positive |
| Pino 3 | IN1- — Channel 1 differential input, negative |
| Pino 4 | REF — Reference voltage pin |
| Pino 5 | REFOUT — Internal reference output |
| Pino 6 | GND — Ground |
| Pino 7 | VDD — Analog 3.3V / 5V supply |
| Pino 8 | GND — Ground |
| Pino 9 | OVDD — Digital interface supply |
| Pino 10 | GND — Ground |
| Pino 11 | CLK+ — Conversion clock, positive (LVDS) |
| Pino 12 | CLK- — Conversion clock, negative (LVDS) |
| Pino 13 | CNV+ — Convert / start, positive (LVDS) |
| Pino 14 | CNV- — Convert / start, negative (LVDS) |
| Pino 15 | GND — Ground |
| Pino 16 | SDO+ — Serial data output, positive (LVDS) |
| Pino 17 | SDO- — Serial data output, negative (LVDS) |
| Pino 18 | SCK+ — Serial clock output, positive (LVDS) |
| Pino 19 | SCK- — Serial clock output, negative (LVDS) |
| Pino 20 | SDI+ — Serial data input, positive (LVDS, daisy chain) |
| Pino 21 | SDI- — Serial data input, negative (LVDS, daisy chain) |
| Pino 22 | BUSY — Conversion busy indicator |
| Pino 23 | GND — Ground |
| Pino 24 | IN2+ — Channel 2 differential input, positive |
| Pino 25 | IN2- — Channel 2 differential input, negative |
| Pino 26 | GND — Ground |
| Pino 27 | VDD — Analog 3.3V / 5V supply |
| Pino 28 | GND — Ground |
Aplicações típicas
LTC2321CUFD-12 é adequado para 6 aplicaçãos: Multi-Phase Motor Current Sensing, Industrial Process Control Data Acquisition, Power Quality and Energy Metering, Medical Imaging Front End, Automatic Test Equipment (ATE) Signal Capture, Vibration and Acoustic Analysis.
Multi-Phase Motor Current Sensing
The LTC2321CUFD-12 is a strong fit for multi-phase motor current sensing because its two channels sample at exactly the same instant (true simultaneous sampling), eliminating the phase-skew error that would otherwise corrupt instantaneous power calculation. Each 12-bit + sign channel at 2 Msps easily digitizes PWM-current waveforms in 50-200 kHz motor drives, while the 8 Vp-p differential input swing interfaces directly to high-side or low-side current-shunt amplifier outputs. Wide common-mode range tolerates the large dv/dt transients typical of MOSFET half-bridges without input saturation.
Recomendado
Industrial Process Control Data Acquisition
In industrial process-control and factory-automation systems, the LTC2321CUFD-12 provides two fast, low-latency analog inputs for digitizing sensor signals such as load-cell outputs, pressure transducers, and valve-position feedback. The SAR architecture delivers deterministic latency, which is critical when the digitized result is fed back into a PID control loop in real time. The wide common-mode range allows the part to accept signals riding on different grounds or bias levels without level-shifting, simplifying the analog front-end in distributed I/O modules.
Recomendado
Power Quality and Energy Metering
Three-phase power-quality analyzers and smart energy meters use the LTC2321CUFD-12 to digitize voltage and current waveforms simultaneously on multiple phases. The 2 Msps per channel sample rate comfortably captures harmonic content up to the 40th harmonic of a 50/60 Hz mains, supporting THD and individual-harmonic analysis per IEC 61000-4-7. The 12-bit + sign dynamic range resolves both the fundamental and low-order harmonics with adequate SNR, while the wide common-mode range directly accepts the scaled output of voltage-divider networks used on 480 V or higher AC lines.
Recomendado
Medical Imaging Front End
Ultrasound and other medical imaging front-ends use the LTC2321CUFD-12 to digitize time-gain compensated (TGC) receive signals from piezoelectric transducer arrays. The 2 Msps simultaneous dual-channel conversion captures two adjacent channels of an aperture at the same moment, preserving phase coherence needed for beamforming. The wide input common-mode range allows AC coupling of TGC outputs without DC biasing networks, while the low noise floor of the SAR front-end preserves small-signal dynamic range - directly improving the achievable image SNR.
Recomendado
Automatic Test Equipment (ATE) Signal Capture
In ATE pin-electronics and mixed-signal test systems, the LTC2321CUFD-12 functions as a high-throughput digitizer for measuring DUT (device-under-test) analog responses with deterministic latency. Two simultaneous 2 Msps channels let a single IC capture both the stimulus and the response in lockstep, or two channels of a differential stimulus signal, without introducing sampling skew. The wide common-mode range accepts a wide range of DUT signal levels without front-end attenuation networks. SAR architecture eliminates the latency variation seen in pipeline ADCs, simplifying stimulus-response timing analysis.
Recomendado
Vibration and Acoustic Analysis
MEMS microphone arrays, vibration sensors, and acoustic emission analyzers use the LTC2321CUFD-12 to digitize two channels of audio-bandwidth data simultaneously, enabling accurate cross-correlation and phase analysis. The 2 Msps per channel rate is well above the Nyquist requirement for 20 kHz audio and most mechanical-vibration bands. SAR architecture provides glitch-free, deterministic single-shot capture of transient events, which is essential for capturing impact or fault signatures. Wide common-mode range accommodates the bias output of integrated MEMS pre-amplifiers.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LTC2321CUFD-12 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LTC2321IUFD-12 | LTC2321HUFD-12 | LTC2321CUFD-12#PBF | LTC2321CUFD-12#TRPBF | LTC2323CUFD-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 28-pin QFN (4x5 mm) | 28-pin QFN (4x5 mm) - same | 28-pin QFN (4x5 mm) - same | 28-pin QFN (4x5 mm) - same | 28-pin QFN (4x5 mm) - same | 28-pin QFN (4x5 mm) - same |
| Resolution | 12-bit + sign | 12-bit + sign | 12-bit + sign | 12-bit + sign | 12-bit + sign | 12-bit + sign |
| Channels | 2 simultaneous | 2 simultaneous | 2 simultaneous | 2 simultaneous | 2 simultaneous | 8 multiplexed (sequential) |
| Sample Rate (per channel) | 2 Msps | 2 Msps | 2 Msps | 2 Msps | 2 Msps | 2 Msps aggregate |
| Operating Temperature | 0C to +70C (C grade) | -40C to +85C (I grade) | -40C to +125C (H grade) | 0C to +70C | 0C to +70C | 0C to +70C |
| Differential Input Range | 8 Vp-p | 8 Vp-p | 8 Vp-p | 8 Vp-p | 8 Vp-p | 8 Vp-p |
| 1-piece Price (USD, as of 2026-10-13) | 8.95 | approximately 9.50 | approximately 11.20 | 8.95 (same die, PBF suffix) | 8.95 (T&R packaging) | approximately 7.60 |
Principais diferenciais
- True dual simultaneous-sampling channels in 28-QFN (vs LTC2323CUFD-12 (8-channel multiplexed))
- Wide 8 Vp-p differential input range with rail-to-rail common-mode (vs LTC2314HTS8-14 (lower input swing))
- SAR architecture with deterministic latency (vs Pipeline ADCs (e.g., AD9228 family))
Notas de projeto
Place the differential RC network (typically 20 ohm series and 47 pF to GND on each input) directly at the IN+ / IN- pins to absorb charge kickback from the internal sampling capacitor. Route IN+ and IN- as a tightly coupled differential pair on the top layer with a continuous ground plane underneath - any mismatch in trace length translates directly into common-mode-to-differential conversion that degrades SNR. The QFN exposed pad must be soldered to a ground copper pour with at least 4 thermal vias for low thermal impedance.
Keep the analog section (inputs, reference, AVDD) physically separated from the LVDS digital section (CLK, CNV, SDO, SCK, SDI) on the PCB. Use separate ground regions joined only at a single point, or split the GND layer into analog and digital halves stitched together near the ADC. The LVDS signals should be 100 ohm differential microstrip with matched length (+/- 5 mil) and DC-balanced termination at the receiver.
Do not apply a noisy, high-impedance clock to the CLK+/CLK- pins - clock jitter directly degrades SNR. Use a low-jitter LVDS clock source (jitter under 5 ps RMS preferred for full 12-bit performance). The wide common-mode input range is a feature, not an excuse to skip anti-alias filtering; always place a properly sized differential RC anti-alias filter ahead of the inputs to prevent out-of-band noise from aliasing into the passband.
Informações de conformidade
PBF suffix denotes lead-free / RoHS compliant. C-grade temperature range (0C to +70C) is commercial; not AEC-Q100 qualified. Not applicable for automotive.
