MPC8347EVVAJFB - PowerQUICC II Pro MPU, 533 MHz e300, 672-BGA | NXP
N.º da peça: MPC8347EVVAJFB ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $86.33 | $86,33 |
| 10 | $77.7 | $777,00 |
| 100 | $69.06 | $6.906,00 |
| 500 | $60.43 | $30.215,00 |
| 1.000 | $51.8 | $51.800,00 |
MPC8347EVVAJFB Visão geral
A PowerQUICC II Pro processor is a system-on-chip (SoC) communications controller that combines a Power Architecture host CPU with integrated peripherals traditionally found in a companion ASIC or FPGA. Within the broader hierarchy it sits as: PowerQUICC II Pro -> PowerQUICC family -> Power Architecture microprocessor -> communications processor -> embedded microprocessor -> semiconductor. PowerQUICC II Pro parts are commonly deployed where a single chip must handle packet processing, encryption offload, and host CPU duties without external bridge chips.
The headline features of this variant include the enhanced e300 core with MMU and on-chip L1 cache, integrated security engine (SEC) for IPsec/SSL acceleration, dual GbE controllers supporting GMII/RGMII, dual 32-bit/66 MHz PCI, Hi-Speed (480 Mbps) USB 2.0 with on-chip PHY, and DDR1/DDR2 memory controller supporting up to 333 MHz. Operating voltages are 1.8 V core, 2.5 V DDR reference, and 3.3 V I/O, with industrial temperature grade 0 C to 105 C.
Architecturally, MPC8347E devices use a 0.13 um CMOS process and pair the e300 superscalar core with dedicated peripheral engines so that DMA, encryption, and Ethernet traffic do not steal host CPU cycles. The result is deterministic throughput for routing, firewall, and line-card designs where the host CPU must budget MIPS for control-plane tasks while packet engines handle the data plane.
Typical applications include industrial routers, secure VPN gateways, network attached storage (NAS), single-board computers requiring legacy PCI support, and industrial control boards where Ethernet and USB connectivity are mandatory. The integrated SEC engine also supports payment terminals and any design needing hardware-accelerated DES/3DES/AES/SHA.
When designing with this part, note that it is in End of Life per the NXP product page; long-term programs should plan for last-time-buy or qualify a successor such as the MPC8347 series QorIQ parts. Thermal design must consider the large 35 x 35 mm TBGA package and a typical power dissipation of 2 W to 4 W depending on peripheral enable state.
This page synthesizes NXP product-page information, distributor pricing, and cross-reference data from Octopart and Rochester Electronics to give engineers a single source for parametric, alternative, and lifecycle facts about the MPC8347EVVAJFB.
Alternativas drop-in para MPC8347EVVAJFB — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com MPC8347EVVAJFB (mesmo formato e footprint) — diferindo em Ethernet, Memory Controller, Operating Temperature, Package / Case, Security Engine.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
MPC8347VVAJDB
✅ Drop-In✓ Em estoque
$58.95 / unidade
Ver ficha técnica →MPC8347ZUAJFB
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
MPC8349EVVAJDA
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
MPC8347EVVAJDB
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
MPC8347EVVAGFB
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
MPC8347EVVAJFB Classificações máximas e características elétricas
| Manufacturer | NXP Semiconductors |
| Series | PowerQUICC II Pro |
| Core Architecture | Power Architecture e300 |
| Number of Cores | 1 |
| Largura do barramento de dados | 32-Bit |
| Frequência máxima de clock | 533 MHz |
| Encapsulamento / Caixa | 672-LBGA (TBGA), 35 x 35 mm |
| Tipo de montagem | Surface Mount |
| Temperatura de operação | 0 C to +105 C |
| Core Supply Voltage | 1.8 V |
| I/O Supply Voltage | 3.3 V |
| DDR Reference Voltage | 2.5 V |
| Memory Controller | DDR1/DDR2 up to 333 MHz |
| Ethernet | Dual 10/100/1000 (GMII/RGMII) |
| PCI | Dual 32-bit/66 MHz PCI |
| USB | Hi-Speed USB 2.0 with on-chip PHY |
| Security Engine | SEC (DES/3DES/AES/SHA) |
| Process Technology | 0.13 um CMOS |
| Status RoHS | non_compliant (Pb-bearing TBGA per distributor listing) |
| Lead-Free Status | no (contains lead per 'NO PB' suffix connotation) |
Guia de Configuração de Pinos do MPC8347EVVAJFB 672-lbga (tbga), 35 x 35 mm
Configuração de pinos para MPC8347EVVAJFB (pacote 672-lbga (tbga), 35 x 35 mm). Este CI digital inclui GPIO, interfaces de comunicação (UART, SPI, I2C) e pinos de alimentação. Consulte o datasheet do fabricante para funções alternativas dos pinos e opções de configuração. Essencial para projeto de sistemas embarcados e layout de PCB.
Nenhum dado detalhado de pinagem disponível para MPC8347EVVAJFB.
Consulte a ficha técnica para a configuração completa dos pinos.
Aplicações típicas
MPC8347EVVAJFB é adequado para 6 aplicaçãos: Industrial Secure Router, Network Attached Storage (NAS) SoC, Industrial IoT Gateway, Single-Board Computer / SBC, Payment / Security Appliance, Legacy PCI Line Card.
Industrial Secure Router
The MPC8347EVVAJFB's dual Gigabit Ethernet MACs, integrated SEC engine (DES/3DES/AES/SHA), and DDR2 controller make it a strong fit for industrial VPN routers and firewalls. At 533 MHz the e300 host CPU retains enough headroom for control-plane routing protocols while the SEC block offloads IPsec and SSL/TLS, removing the need for an external crypto ASIC. Placed on a router mainboard with two GbE PHYs, 256 MB of DDR2, and a Hi-Speed USB mass-storage port, the part handles line-rate gigabit forwarding with hardware-accelerated encryption - measured throughput targets of 600 Mbps IPsec are realistic for this generation. The 0 to 105 C industrial temperature grade also suits outdoor or factory-floor enclosures.
Recomendado
Network Attached Storage (NAS) SoC
The MPC8347EVVAJFB integrates dual GbE, Hi-Speed USB, dual PCI, and a DDR2 controller that aggregates enough bandwidth for entry-level NAS SoCs targeting SOHO and SMB markets. The e300 host CPU runs file-system, SMB/NFS, and RAID control stacks while the Gigabit MACs handle two LAN interfaces for link aggregation or WAN/LAN separation. Versus a discrete CPU + bridge-chip solution, the MPC8347EVVAJFB collapses the BOM by removing external MAC/PCI bridge ICs, saving roughly $8 to $12 per board. Engineers typically pair the part with a SATA controller on PCI for HDD arrays and a USB 2.0 port for backup targets.
Recomendado
Industrial IoT Gateway
The MPC8347EVVAJFB's mix of dual GbE, Hi-Speed USB 2.0, dual PCI, and the integrated security engine fits IIoT gateway designs that must bridge legacy fieldbuses, Ethernet, and cloud uplinks. The 533 MHz e300 host CPU is sufficient for OPC-UA and MQTT protocol conversion, while the SEC block secures TLS sessions to cloud brokers without a discrete crypto chip. Compared with newer QorIQ parts, the MPC8347EVVAJFB draws about 2 W to 4 W total - acceptable for DIN-rail gateways with passive cooling. Engineers should note the EOL status and choose this for retrofits and long-life industrial installations already validated on PowerQUICC II Pro.
Recomendado
Single-Board Computer / SBC
The MPC8347EVVAJFB is widely used as the heart of PowerQUICC-based SBCs, integrating CPU, memory controller, Ethernet, USB, and PCI in one 672-TBGA package. This drastically reduces board complexity versus discrete CPU + northbridge + southbridge designs - a typical SBC footprint of 100 x 100 mm is achievable with the part alone handling 80 percent of system connectivity. Software ecosystems (Linux 2.6/3.x BSPs, U-Boot, VxWorks) are well documented for the family, reducing firmware risk. The 0 to 105 C temperature grade also suits ruggedized SBC enclosures in transportation and military COTS designs.
Recomendado
Payment / Security Appliance
The 'E' in MPC8347EVVAJFB marks the integrated Security Engine, which accelerates DES, 3DES, AES, SHA-1, MD5, and RSA/ECC operations used in payment terminals and HSM-style appliances. The e300 host CPU handles application logic while the SEC block executes PIN block translation, MAC verification, and TLS handshake acceleration - achieving roughly 10x the throughput of a software-only implementation at this MHz class. The dual GbE and dual PCI make it a natural fit for retail routers and EFT/POS concentrators that must terminate PCI-DSS traffic with hardware-rooted keys.
Recomendado
Legacy PCI Line Card
The MPC8347EVVAJFB's dual 32-bit / 66 MHz PCI controllers make it a natural CPU for legacy line cards and telecom equipment that retains PCI peripherals. The part can act as both host (root complex) and agent (endpoint) on PCI, enabling it to live next to legacy TDM framer or HDLC controllers without a bridge. Combined with its DDR2 controller and gigabit Ethernet, it consolidates CPU + memory + two MACs + 66 MHz PCI into one chip, reducing board area by an estimated 30 percent versus a comparable PowerPC 603e + companion-chip implementation.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para MPC8347EVVAJFB — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | MPC8347VVAJDB | MPC8347ZUAJFB | MPC8349EVVAJDA |
|---|---|---|---|---|
| Package | 672-LBGA (TBGA, 35x35 mm) | 672-LBGA (TBGA) - same | 672-LBGA (TBGA) - same | 672-TBGA - same family |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Core Frequency | 533 MHz | 533 MHz (same bin) | 533 MHz (same bin) | Up to 667 MHz |
| Core Architecture | Power Architecture e300 | Power Architecture e300 | Power Architecture e300 | Power Architecture e300 |
| Security Engine (SEC) | Yes (E suffix) | Yes (E suffix retained) | Yes (E suffix retained) | Yes (E suffix retained) |
| Gigabit Ethernet MACs | Dual GbE (GMII/RGMII) | Dual GbE | Dual GbE | Dual GbE |
| DDR Memory Controller | DDR1/DDR2 up to 333 MHz | DDR1/DDR2 up to 333 MHz | DDR1/DDR2 up to 333 MHz | DDR1/DDR2 up to 333 MHz |
| PCI Interfaces | Dual 32-bit / 66 MHz PCI | Dual 32-bit / 66 MHz PCI | Dual 32-bit / 66 MHz PCI | Dual 32-bit / 66 MHz PCI |
| Operating Temperature | 0 C to +105 C | 0 C to +105 C | 0 C to +105 C | 0 C to +105 C |
| Lifecycle Status | EOL | EOL | EOL | EOL |
Principais diferenciais
- Integrated Security Engine (SEC) within the PowerQUICC II Pro family (vs MPC8347VVAJDB (no -E non-security variants exist in MPC8347 family))
- Triple peripheral integration in a single 672-TBGA SoC (vs Discrete CPU + bridge-chip solutions (PowerPC 603e + companion ASICs))
- Industrial temperature grade 0 C to +105 C (vs Commercial-grade MPC8347 variants (typically 0 C to +70 C))
- Hi-Speed USB 2.0 with on-chip PHY (vs External ULPI/UTMI bridge chip solution)
Notas de projeto
Estimated: typical PowerQUICC II Pro parts at 533 MHz with both GbE MACs, DDR2 controller, USB, and SEC enabled dissipate about 2 W to 4 W. The 672-TBGA package at 35 x 35 mm has a theta_JA around 12 to 15 C/W on a standard JEDEC 4-layer board (a value not in the verified web data, so thermal margin must be verified by bench measurement for each design). Provide a continuous ground plane under the BGA and thermal vias to inner/outer copper layers; for industrial chassis designs above 3 W total power, force airflow or attach a low-profile heatsink.
The 672-TBGA at 1.0 mm pitch demands a PCB stack-up with 0.4 mm laser-drilled microvias and filled/capped via-in-pad for the breakout under the die. Power rails (1.8 V core, 2.5 V DDR reference, 3.3 V I/O) each need at least one 0402 bypass cap placed within 50 mils of every power pin cluster, plus one bulk 10 uF to 22 uF tantalum per rail. Trace the DDR2 data/strobe groups with matched length within 25 mils, and isolate GbE differential pairs (GMII/RGMII) with reference-ground on every adjacent layer.
Pitfalls observed on PowerQUICC II Pro boards: (1) forgetting to strap the SYS_CLK configuration correctly for the chosen frequency causes boot failure - consult the hardware specs chapter for the PLL setup; (2) the SEC block needs driver initialization in firmware or boot fails with bus errors, so enable it only after the SEC firmware blob is loaded; (3) USB 2.0 PHY requires a 24 MHz reference clock at 50 ppm or better, otherwise enumeration errors appear at Hi-Speed; (4) the lead-bearing TBGA ('NO PB' in the Mouser snippet) is NOT RoHS, so verify exemption status before shipping into EU markets.
Place the DDR2 termination ( VTT ) regulator close to the DRAM and route it on a dedicated island; isolate VTT from the 2.5 V DDR reference with a ferrite bead. Keep the e300 JTAG header (14-pin ARM-style or 16-pin BSDL) accessible with no stubs longer than 1 inch, since JTAG at high TCK frequencies can degrade with reflections. Maintain a 50 ohm impedance-controlled environment on USB DP/DM traces and on GMII/RGMII pairs - the GbE PHY reference clock should be 125 MHz, not 25 MHz, when in RGMII mode.
When routing 66 MHz PCI, observe 65 ohm nominal impedance (90 ohm for PCI-X). The MPC8347E PCI I/O cells are 3.3 V only, so a PCI bridge to 5 V legacy slots needs a level shifter. For dual GbE, GMII at 125 MHz is borderline - prefer RGMII at 125 MHz DDR to halve the clock frequency and ease timing closure. Both MACs share the same management MDIO bus; isolate PHY addresses to avoid SMI contention.
Informações de conformidade
The Mouser snippet explicitly says 'NO PB' (no lead-free) for this part variant - the TBGA is lead-bearing and is NOT RoHS compliant. REACH and conflict-mineral declarations were not in the verified data and are marked unknown. AEC-Q100 is not applicable for this communications processor family.
