N25Q128A13ESF40G - 128Mb SPI NOR Flash, 108 MHz, SO-16
N.º da peça: N25Q128A13ESF40G ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $1.45 | $1,45 |
| 10 | $1.28 | $12,80 |
| 100 | $1.12 | $112,00 |
| 500 | $0.95 | $475,00 |
| 1.000 | $0.78 | $780,00 |
| 2.500 | $0.68 | $1.700,00 |
N25Q128A13ESF40G Visão geral
A NOR flash is a non-volatile memory that supports random byte-level read access and byte-level program/erase, in contrast to NAND flash which is read in large pages. Serial NOR flash devices such as the N25Q128A13ESF40G connect over a low-pin-count SPI bus, dramatically simplifying board routing while preserving the byte-addressable random read that makes NOR ideal for code storage. Within the memory hierarchy, N25Q128A13ESF40G sits between external boot ROM and the MCU/MPU's internal SRAM, providing firmware storage that the host CPU executes in-place via XiP.
Key features include a 108 MHz SPI clock with Dual/Quad I/O instruction extensions, 4 KB sub-sector erase granularity, advanced write protection with top/bottom block lock and OTP security area, 100k program/erase cycles endurance per sector, and 20-year data retention. The device also supports single 1.7 V internal core voltage operation from a single 3 V external rail. 128 Mb density provides ample space for bootloaders, OS images, and configuration data in space-constrained designs.
Typical applications include firmware boot storage for STM32/i.MX RT/micro:bit-class MCUs, asset tracking and IoT edge nodes, automotive infotainment boot partitions, industrial PLC firmware storage, and consumer electronics such as set-top boxes, printers, and Wi-Fi modules. The 16-pin SOIC-16 wide-body (208 mil) package is hand-solderable and inspectable, well suited for production and rework.
Designers should note that the 'F' suffix in 'ESF40G' indicates 108 MHz Quad SPI performance with a 4-second erase / 108 MHz Quad SPI mode; the 'G' suffix indicates lead-free / Pb-free / RoHS-compliant terminal finish. When migrating from parallel NOR to this part, recalculate access latencies since SPI throughput is lower per pin but Quad SPI closes much of the gap. Always honor the maximum 108 MHz SPI clock and respect tVSL/Vcc ramp requirements during power-up.
Alternativas drop-in para N25Q128A13ESF40G — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com N25Q128A13ESF40G (mesmo formato e footprint) — diferindo em Bus Interface, Data Retention, Memory Type, Operating Temperature, Package.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
N25Q128A13ESF40F
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
N25Q128A13ESE40G
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
N25Q128A13ESF40E
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
W25Q128JVSIQ
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
GD25Q128CSIG
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
MX25L12835FM2I-10G
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
IS25LP128-JBLE
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
N25Q128A13ESF40G Classificações máximas e características elétricas
| Tipo de memória | Non-volatile NOR Flash |
| Tamanho da memória | 128 Mbit (16 MB) |
| Organização da memória | 128M/64M/32M x 1/2/4 bit |
| Bus Interface | SPI (Serial, Multi-I/O) |
| Max SPI Clock Frequency | 108 MHz |
| Operating Voltage (Vcc) | 2.7 V to 3.6 V |
| Sector Erase Size | 4 KB sub-sector |
| Program/Erase Endurance | 100,000 cycles per sector |
| Data Retention | 20 years (per Micron datasheet) |
| XiP (Execute-in-Place) | Yes |
| Encapsulamento | SO-16 (208 mil wide-body SOIC) |
| Temperatura de operação | -40C to +85C |
| Lead-Free / RoHS | Yes ('G' suffix) |
| Tipo de montagem | Surface Mount |
| Technology Node | 65 nm NOR |
Configuração de pinos do N25Q128A13ESF40G
| Pino 1 | CS# — Chip Select (active low) |
| Pino 2 | SO/SIO1 — Serial Output / Serial I/O 1 (Quad SPI data) |
| Pino 3 | WP#/SIO2 — Write Protect (active low) / Serial I/O 2 (Quad SPI data) |
| Pino 4 | GND — Ground |
| Pino 5 | SI/SIO0 — Serial Input / Serial I/O 0 (Quad SPI data) |
| Pino 6 | CLK — SPI Clock |
| Pino 7 | HOLD#/RESET#/SIO3 — Hold/Reset (active low) / Serial I/O 3 (Quad SPI data) |
| Pino 8 | VCC — Power Supply (2.7 V to 3.6 V) |
| Pino 9 | NC — Not connected (per datasheet) |
| Pino 10 | NC — Not connected (per datasheet) |
| Pino 11 | NC — Not connected (per datasheet) |
| Pino 12 | NC — Not connected (per datasheet) |
| Pino 13 | NC — Not connected (per datasheet) |
| Pino 14 | NC — Not connected (per datasheet) |
| Pino 15 | NC — Not connected (per datasheet) |
| Pino 16 | NC — Not connected (per datasheet) |
Aplicações típicas
N25Q128A13ESF40G é adequado para 6 aplicaçãos: STM32 / i.MX RT External Boot Flash (XiP), Industrial IoT Edge Sensor Hubs, Automotive Infotainment Boot Partition, Consumer Wi-Fi/BLE Module Firmware, PLC / Industrial Control Firmware Storage, Set-Top Box / Smart TV Boot ROM.
STM32 / i.MX RT External Boot Flash (XiP)
The N25Q128A13ESF40G serves as external boot storage for STM32H7, STM32F7, and NXP i.MX RT1062/1167 microcontrollers that lack sufficient internal flash for full firmware images. With 108 MHz Quad SPI throughput and execute-in-place (XiP) capability, the host MCU fetches code directly from the N25Q128A13ESF40G at 50+ MB/s sustained, eliminating the need to shadow-load into SRAM. The 16 MB density accommodates bootloader (32 KB), active firmware (12 MB), and OTA staging partition (4 MB) in typical layouts. Designers route CS#, CLK, SI/SIO0, SO/SIO1, WP#/SIO2, HOLD#/SIO3 to the MCU's Quad SPI controller, with 100 ohm series termination on CLK for signal integrity on long traces.
Recomendado
Industrial IoT Edge Sensor Hubs
Industrial IoT edge gateways and sensor hubs use the N25Q128A13ESF40G for local firmware storage and data logging in factories, smart meters, and outdoor LoRaWAN deployments. The 16 MB capacity stores the Linux/RTOS image, configuration database, and several hours of buffered sensor data, while the -40C to +85C operating range meets industrial temperature requirements. Per the Micron datasheet, the device's 100k P/E endurance per 4 KB sector supports years of OTA firmware updates, and the 20-year data retention ensures calibration constants survive in-field for the product lifetime without battery backup.
Recomendado
Automotive Infotainment Boot Partition
Automotive infotainment systems use the N25Q128A13ESF40G (or AEC-Q100-qualified sibling) to store the head-unit bootloader and recovery image outside the main SoC. Per the Micron product line, AEC-Q100-qualified N25Q variants exist for IVI (in-vehicle infotainment) applications requiring -40C to +85C or +105C grades. The Quad SPI interface allows fast boot recovery in under 2 seconds, and the OTP security area can hold cryptographic keys for secure boot verification. Designers place the part on a dedicated SPI bus isolated from the radio DSP to prevent boot-time contention.
Recomendado
Consumer Wi-Fi/BLE Module Firmware
Wi-Fi 6, BLE 5.3, and LoRa modules rely on the N25Q128A13ESF40G for firmware and provisioning data storage, where the small 16-pin SOIC-16 wide-body footprint simplifies integration into the module's limited board area. Per Micron's datasheet, the 108 MHz Quad SPI bandwidth allows over-the-air (OTA) firmware updates to land directly into the N25Q with minimal downtime. The 'G' suffix verifies RoHS compliance for consumer electronics shipping into EU markets, while the 4 KB sub-sector erase granularity allows small OTA delta updates without erasing the entire firmware region.
Recomendado
PLC / Industrial Control Firmware Storage
Programmable logic controllers (PLCs) and industrial HMIs use the N25Q128A13ESF40G for ladder-logic program storage and HMI graphics asset retention. The 16 MB density is sufficient for complex PLC programs (1-4 MB) plus HMI screens (2-8 MB) plus audit logs, all in a single SOIC-16 device. Per the Micron datasheet, the OTP security area allows OEMs to lock calibration data and OEM branding assets against field modification. The Quad SPI interface allows fast screen-update transfers during HMI animation without affecting PLC scan-time determinism.
Recomendado
Set-Top Box / Smart TV Boot ROM
Set-top boxes and smart TV mainboards use the N25Q128A13ESF40G as boot ROM alongside the main SoC's NAND or eMMC storage. Per Micron documentation, the 108 MHz Quad SPI interface enables sub-second boot recovery when the primary OS image is corrupted, a critical feature for always-on consumer devices. The 20-year retention ensures the bootloader survives the product's full service life without backup, and the wide-body SOIC-16 package simplifies post-production firmware programming during manufacturing flow.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para N25Q128A13ESF40G — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | N25Q128A13ESF40F | N25Q128A13ESE40G | W25Q128JVSIQ | GD25Q128CSIG | MX25L12835FM2I-10G | IS25LP128-JBLE |
|---|---|---|---|---|---|---|---|
| Brand | Micron Technology | Micron Technology | Micron Technology | Winbond | GigaDevice | Macronix | ISSI |
| Package | SOIC-16 (208 mil) | SOIC-16 (208 mil) | SOIC-16 (208 mil) | SOIC-16 (300 mil) | SOIC-16 (208 mil) | SOIC-16 (300 mil) | SOIC-16 (300 mil) |
| Memory Density | 128 Mbit (16 MB) | 128 Mbit (16 MB) | 128 Mbit (16 MB) | 128 Mbit (16 MB) | 128 Mbit (16 MB) | 128 Mbit (16 MB) | 128 Mbit (16 MB) |
| Max SPI Clock | 108 MHz | 108 MHz | 108 MHz | 133 MHz | 108 MHz | 104 MHz | 133 MHz |
| Operating Voltage | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V |
| Sector Erase Size | 4 KB sub-sector | 4 KB sub-sector | 4 KB sub-sector | 4 KB sub-sector | 4 KB sub-sector | 4 KB sub-sector | 4 KB sub-sector |
| P/E Endurance | 100,000 cycles/sector | 100,000 cycles/sector | 100,000 cycles/sector | 100,000 cycles/sector | 100,000 cycles/sector | 100,000 cycles/sector | 100,000 cycles/sector |
| Execute-in-Place (XiP) | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Lead-Free / RoHS | Yes ('G' suffix) | Yes | Yes | Yes | Yes | Yes | Yes |
Principais diferenciais
- Wide-body 208 mil SOIC-16 footprint (vs W25Q128JVSIQ)
- First-source Micron NOR with Quad SPI XiP at 108 MHz (vs GD25Q128CSIG)
- Native lead-free finish (G suffix) (vs N25Q128A13ESF40E)
Notas de projeto
VCC ramp time is critical for the N25Q128A13ESF40G to properly initialize its status register. Per the Micron datasheet, ensure the VCC ramp rate respects the tVSL specification during power-on; a too-slow ramp can leave the status register in an undefined state, which manifests as the first read returning incorrect data. Place a 0.1 uF decoupling capacitor within 5 mm of the VCC pin, with bulk 4.7 uF near the part, and verify that upstream LDO slew rate satisfies the datasheet minimum VCC rise time.
At 108 MHz SPI clock rates, signal integrity on the SPI bus matters. Place 33 ohm series termination resistors on CLK, CS#, SI, and SO lines close to the MCU driver, with PCB trace lengths matched within 1 cm. Per the Micron datasheet, hold the CS# signal high during Quad SPI mode to prevent bus contention. Use a ground reference plane on layer 2 directly beneath the SPI traces to control impedance to 50 ohms and minimize crosstalk from adjacent signals.
Do not confuse the 208 mil SOIC-16 (N25Q128A13ESF40G) with the 300 mil SOIC-16 (W25Q128JVSIQ / MX25L12835FM2I-10G / IS25LP128-JBLE). The pin pitch is identical (1.27 mm) but the body width differs, so PCB land patterns are not interchangeable. Per Micron cross-reference data, when migrating cross-brand from W25Q to N25Q, also note that the JEDEC manufacturer ID (20h Micron vs EFh Winbond) must be updated in firmware. Status register bit definitions differ slightly between vendors; verify BP bits and lock bits match your write-protection requirements.
Route the SPI bus with 50 ohm controlled impedance on a dedicated routing layer. Per Micron application notes, keep the SPI bus traces under 50 mm total length to avoid clock-distortion issues at 108 MHz. Place the N25Q128A13ESF40G within 25 mm of the MCU, and add a 100 kohm pull-up on CS# to prevent floating-chip-select during MCU reset. The HOLD#/RESET#/SIO3 pin can be tied to VCC through 10 kohm if the hold/reset feature is not used.
Informações de conformidade
RoHS and REACH compliance per Micron product page. 'G' suffix in part number denotes lead-free finish. Not AEC-Q100 qualified - commercial / industrial grade only (-40C to +85C). For automotive applications, request the AEC-Q100-qualified N25Q family variant from Micron.
