PIC18F4525-I/ML - 48KB Flash 8-bit MCU, 44-QFN | Microchip
N.º da peça: PIC18F4525-I/ML ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $7.85 | $7,85 |
| 10 | $7.06 | $70,60 |
| 100 | $6.28 | $628,00 |
| 500 | $5.65 | $2.825,00 |
| 1.000 | $5.02 | $5.020,00 |
PIC18F4525-I/ML Visão geral
A PIC18 microcontroller is a Harvard-architecture 8-bit RISC processor from Microchip's PIC family, positioned between baseline PIC10/12/16 devices and the 16-bit dsPIC/PIC24 families. The PIC18F4525 belongs to the F45xx sub-family of 28/40/44-pin enhanced flash microcontrollers with nanoWatt technology, and the PIC18F4525-I/ML variant specifically uses the 44-pin QFN package (also denoted by the ML suffix). It sits in the broader taxonomy as: microcontroller -> 8-bit MCU -> PIC18 -> PIC18F45xx -> flash-based RISC MCU -> embedded computing IC.
Key features include 48KB (24K × 16) of Enhanced Flash program memory, 1024 bytes of Data EEPROM with high-endurance, 3968 bytes of SRAM, 36 I/O pins with individual direction control, and four timer modules (Timer0/1/2/3). Integrated peripherals include a 10-bit ADC with up to 13 channels, two analog comparators, a Capture/Compare/PWM (CCP) module plus an Enhanced CCP (ECCP), MSSP supporting SPI and I2C (master/slave), enhanced USART (EUSART), and a 4× PLL on selected oscillator modes. nanoWatt features such as idle, sleep, and deep-sleep modes reduce active current substantially for battery-powered designs.
Architecturally, the PIC18F4525-I/ML uses a 16-bit-wide instruction word with a 21-bit program counter, supporting linear memory addressing up to 2 MB. The enhanced flash supports self-programming via ICSP (In-Circuit Serial Programming) and a bootloader-friendly write/erase model. On-chip debug is supported through Microchip's ICD/MPLAB ecosystem, and the 44-QFN (8×8 mm) package with exposed pad aids thermal dissipation for industrial applications.
Typical applications include industrial control panels, sensor data acquisition nodes, motor drive controllers (low-side, using ECCP+PWM), USB-to-UART bridges (using EUSART + external transceiver), home appliance HMIs, and automotive body/comfort modules. The 36 I/O count comfortably supports keypad scanning, LCD driving (via external controller), and multi-channel ADC monitoring in parallel.
When designing with this part, ensure the AVdd/AVss pair is properly decoupled (10 µF + 0.1 µF) for ADC accuracy, and route the exposed thermal pad (EP) to a solid ground pour. Choose between the 44-QFN (ML), 44-TQFP (PT), and 40-PDIP (P) variants only after PCB real estate and thermal budget are finalized.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Alternativas drop-in para PIC18F4525-I/ML — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com PIC18F4525-I/ML (mesmo formato e footprint) — diferindo em Package, Operating Temperature, Timers, Maximum CPU Speed, Program Memory (Flash).
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
PIC18F4525T-I/ML
✅ Drop-In✓ Em estoque
$5.8 / unidade
Ver ficha técnica →PIC18F4620-I/ML
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
PIC18F4525-I/PT
✅ Drop-In✓ Em estoque
$4.18 / unidade
Ver ficha técnica →PIC18F4523T-I/ML
✅ Drop-In✓ Em estoque
$4.41 / unidade
Ver ficha técnica →PIC18F45K22-I/ML
✅ Drop-In✓ Em estoque
$2.65 / unidade
Ver ficha técnica →PIC18F4420T-I/ML
✅ Drop-In✓ Em estoque
$2.65 / unidade
Ver ficha técnica →PIC18F4525-I/ML Classificações máximas e características elétricas
| Product Type | 8-bit RISC Microcontroller |
| Family | PIC18F45xx (28/40/44-pin Enhanced Flash) |
| Program Memory (Flash) | 48 KB (24K x 16) |
| Data SRAM | 3968 bytes |
| Data EEPROM | 1024 bytes |
| Maximum CPU Speed | 40 MHz |
| Instruction Cycle Time | 200 ns at 20 MHz; 100 ns at 40 MHz (with 4x PLL) |
| Supply Voltage (VDD) | 4.2 V to 5.5 V |
| I/O Pins | 36 |
| ADC | 10-bit, up to 13 channels |
| Timers | Timer0, Timer1, Timer2, Timer3 |
| Communication Peripherals | EUSART, MSSP (SPI / I2C master & slave) |
| Capture/Compare/PWM | 1 CCP + 1 ECCP module |
| Analog Comparators | 2 |
| Encapsulamento | 44-pin QFN (ML), 8x8 mm with exposed pad |
| Operating Temperature (Industrial) | -40 C to +85 C |
| Status RoHS | Compliant |
| Lead-Free | Yes |
| Tipo de montagem | Surface Mount |
| Programming/Debug | ICSP via MPLAB ICD / PICkit |
Configuração de pinos do PIC18F4525-I/ML
| Pino 1 | MCLR/RE3 — Master Clear (reset) input; also PORTE bit 3 |
| Pino 2 | RA0/AN0 — PORTA bit 0; analog input 0 |
| Pino 3 | RA1/AN1 — PORTA bit 1; analog input 1 |
| Pino 4 | RA2/AN2/VREF- — PORTA bit 2; analog input 2; ADC VREF- |
| Pino 5 | RA3/AN3/VREF+ — PORTA bit 3; analog input 3; ADC VREF+ |
| Pino 6 | RA4/T0CKI — PORTA bit 4; Timer0 clock input |
| Pino 7 | RA5/AN4/SS — PORTA bit 5; analog input 4; SPI slave select |
| Pino 8 | RE0/RD/AN5 — PORTE bit 0; read control for parallel port; analog input 5 |
| Pino 9 | RE1/WR/AN6 — PORTE bit 1; write control; analog input 6 |
| Pino 10 | RE2/CS/AN7 — PORTE bit 2; chip select; analog input 7 |
| Pino 11 | VDD — Positive supply for digital logic |
| Pino 12 | VSS — Digital ground |
| Pino 13 | OSC1/CLKI — Crystal/Resonator pin 1 or external clock in |
| Pino 14 | OSC2/CLKO — Crystal/Resonator pin 2 or clock out |
| Pino 15 | RC0/T1OSO/T1CKI — PORTC bit 0; Timer1 oscillator out / clock in |
| Pino 16 | RC1/T1OSI/CCP2 — PORTC bit 1; Timer1 oscillator in; CCP2 PWM output |
| Pino 17 | RC2/CCP1 — PORTC bit 2; CCP1 PWM output |
| Pino 18 | RC3/SCK/SCL — PORTC bit 3; SPI clock; I2C clock |
| Pino 19 | RC4/SDI/SDA — PORTC bit 4; SPI data in; I2C data |
| Pino 20 | RC5/SDO — PORTC bit 5; SPI data out |
| Pino 21 | RC6/TX/CK — PORTC bit 6; EUSART TX / clock |
| Pino 22 | RC7/RX/DT — PORTC bit 7; EUSART RX / data |
| Pino 23 | RD0/PSP0 — PORTD bit 0; Parallel Slave Port data 0 |
| Pino 24 | RD1/PSP1 — PORTD bit 1; PSP data 1 |
| Pino 25 | RD2/PSP2 — PORTD bit 2; PSP data 2 |
| Pino 26 | RD3/PSP3 — PORTD bit 3; PSP data 3 |
| Pino 27 | RD4/PSP4 — PORTD bit 4; PSP data 4 |
| Pino 28 | RD5/PSP5 — PORTD bit 5; PSP data 5 |
| Pino 29 | RD6/PSP6 — PORTD bit 6; PSP data 6 |
| Pino 30 | RD7/PSP7 — PORTD bit 7; PSP data 7 |
| Pino 31 | VSS — Digital ground |
| Pino 32 | VDD — Positive supply for digital logic |
| Pino 33 | RB0/INT0/FLT0 — PORTB bit 0; external interrupt 0; PWM fault input |
| Pino 34 | RB1/INT1 — PORTB bit 1; external interrupt 1 |
| Pino 35 | RB2/INT2 — PORTB bit 2; external interrupt 2 |
| Pino 36 | RB3/INT3/CCP2 — PORTB bit 3; external interrupt 3; alternate CCP2 |
| Pino 37 | RB4/KBI0 — PORTB bit 4; interrupt-on-change |
| Pino 38 | RB5/KBI1/PGM — PORTB bit 5; interrupt-on-change; LVP programming |
| Pino 39 | RB6/KBI2/PGC — PORTB bit 6; interrupt-on-change; ICSP clock |
| Pino 40 | RB7/KBI3/PGD — PORTB bit 7; interrupt-on-change; ICSP data |
| Pino 41 | AVSS — Analog ground |
| Pino 42 | AVDD — Analog supply (must be tied to VDD) |
| Pino 43 | AN8 — Analog input 8 |
| Pino 44 | AN9 — Analog input 9 |
Aplicações típicas
PIC18F4525-I/ML é adequado para 6 aplicaçãos: Industrial Sensor Data Acquisition Node, Motor Control (BLDC / Stepper Front-End), USB-to-UART Bridge / ISP Programmer Dongle, Home Appliance HMI (Display + Keypad), Automotive Body / Comfort Module, Educational / Development Platform.
Industrial Sensor Data Acquisition Node
The PIC18F4525-I/ML is well-suited to multi-channel sensor DAQ nodes where its 10-bit ADC with up to 13 channels can sample temperature, pressure, and current sensors in parallel. The 48 KB Enhanced Flash comfortably hosts Modbus RTU or CANopen stacks, while the 1024-byte Data EEPROM retains calibration constants across power cycles. Running at 40 MHz, it can poll 13 channels at 1 kHz each with CPU headroom for filtering, and the 3968-byte SRAM holds a circular sample buffer without DMA overhead. nanoWatt sleep mode lets the unit idle below 1 µA between acquisition bursts, critical for battery-powered field instrumentation. The exposed thermal pad of the 44-QFN (ML) package is essential when 8-10 channels are sampled continuously at full speed.
Recomendado
Motor Control (BLDC / Stepper Front-End)
With its Enhanced CCP (ECCP) module supporting full-bridge PWM with auto-shutdown and programmable dead-band, the PIC18F4525-I/ML can drive the gate-driver front-end of a small BLDC or stepper motor. The 40 MHz CPU closes PID current loops at 20 kHz PWM, leaving enough MIPS for trapezoidal commutation tables in Flash. The two analog comparators enable hardware overcurrent protection that bypasses the CPU, while the EUSART streams telemetry back to a host controller. For low-voltage 24 V brushless drives up to ~2 A, the 44-QFN (ML) thermal pad handles the ~150 mW CPU dissipation cleanly. Designers moving up in current add a discrete gate driver such as the MCP8024 between the F4525 and the FET bridge.
Recomendado
USB-to-UART Bridge / ISP Programmer Dongle
Using the on-chip EUSART plus an external USB-to-UART bridge such as the MCP2200 or MCP2221, the PIC18F4525-I/ML can act as an in-system programmer or protocol converter for legacy RS-232 equipment. Its 48 KB Flash holds a full command parser plus ICSP host firmware, and the 3968-byte SRAM supports a 1 KB line buffer plus packet reassembly. The MSSP in SPI master mode re-targets firmware into external memory-mapped devices, while the ECCP generates the ICSP clock. The 44-QFN (ML) package keeps the dongle footprint under 1 cm², ideal for field-service tools. nanoWatt sleep mode drops idle current below 1 µA, allowing bus-powered operation from the USB VBUS line through an LDO.
Recomendado
Home Appliance HMI (Display + Keypad)
The PIC18F4525-I/ML drives a character LCD (via 4-bit parallel interface on PORTD), scans a 4×4 matrix keypad on PORTB, and runs the user-interface state machine from its 48 KB Flash. The 36 I/O pins comfortably support 8 LCD data lines, 8 keypad rows/columns, 4 status LEDs, 2 buzzer PWMs, and a UART link to the main appliance controller. The two analog comparators handle over-temperature and water-level detection without burdening the ADC. EUSART runs the diagnostic interface back to a service tool. The 44-QFN (ML) footprint fits behind a sealed membrane keypad, and its -40 to +85 C rating covers refrigerator/freezer and oven-control environments.
Recomendado
Automotive Body / Comfort Module
Although the PIC18F4525-I/ML is not AEC-Q100 qualified, it is widely used in non-safety automotive body modules such as lighting controllers, window lifters (low-current), and HVAC flap drivers at 12 V nominal. The on-chip 10-bit ADC reads 4-8 temperature or position sensors while ECCP drives the actuator PWMs. The MSSP-SPI bus connects to a CAN transceiver (e.g., MCP2515) for body-network communication. The 1024-byte EEPROM stores per-unit trim and diagnostic trouble codes, surviving key-cycle battery disconnects. For designs that must meet AEC-Q100, migrate to the PIC18F45K22-I/ML which is automotive-grade in the same 44-QFN footprint.
Recomendado
Educational / Development Platform
The PIC18F4525-I/ML is a staple of undergraduate embedded-systems labs because it combines the legacy PIC18 instruction set (great teaching tool) with modern peripherals including USB-via-bridge, ADC, PWM, and EUSART. Its 48 KB Flash accepts the full Microchip application-library firmware, including TCP/IP through the MLA, USB device stack, and graphics libraries. The 44-QFN (ML) package is supported on Microchip's PIC18F46J53/PIC18F45K22 Explorer Boards as well as many third-party QFN44-to-DIP adapters used in classrooms. The exposed pad aids thermal management during lab experiments with full 40 MHz operation and continuous ADC sampling.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para PIC18F4525-I/ML — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | PIC18F4525T-I/ML | PIC18F4620-I/ML | PIC18F4525-I/PT | PIC18F4523T-I/ML | PIC18F45K22-I/ML |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 44-QFN (ML) | 44-QFN (ML) - same | 44-QFN (ML) - same | 44-TQFP (PT) - same die | 44-QFN (ML) - same | 44-QFN (ML) - same |
| Flash | 48 KB | 48 KB | 64 KB | 48 KB | 32 KB | 32 KB |
| SRAM | 3968 B | 3968 B | 3986 B | 3968 B | 1536 B | 1536 B |
| EEPROM | 1024 B | 1024 B | 1024 B | 1024 B | 256 B | 256 B |
| Max CPU Speed | 40 MHz | 40 MHz | 40 MHz | 40 MHz | 40 MHz | 64 MHz |
| I/O Pins | 36 | 36 | 36 | 36 | 36 | 36 |
| ADC | 10-bit, 13 ch | 10-bit, 13 ch | 10-bit, 13 ch | 10-bit, 13 ch | 10-bit, 13 ch | 10-bit, 28 ch |
| Supply Voltage | 4.2 - 5.5 V | 4.2 - 5.5 V | 4.2 - 5.5 V | 4.2 - 5.5 V | 4.2 - 5.5 V | 1.8 - 5.5 V (XLP) |
Principais diferenciais
- Larger Data EEPROM and SRAM than PIC18F4523T-I/ML (vs PIC18F4523T-I/ML)
- Drop-in upgrade path to 64 KB Flash on same 44-QFN footprint (vs PIC18F4620-I/ML)
- Same die available in TQFP for hand-soldered prototypes (vs PIC18F4525-I/PT)
- Mature flash and toolchain ecosystem (vs PIC18F45K22-I/ML)
Notas de projeto
Decouple the four power pins (pin 11, pin 32 = VDD digital; pin 42 = AVDD; pin 12, pin 31 = VSS digital; pin 41 = AVSS) with a 10 µF bulk plus 0.1 µF ceramic placed within 5 mm of each pair. Tie AVDD to VDD and AVSS to VSS through a ferrite bead if the ADC samples high-impedance sources, to suppress switching noise coupling from the digital rails. Estimated: at 40 MHz and 5.0 V the core draws approximately 16 mA (per Microchip PIC18F4525 datasheet DC characteristics), so the 0.1 µF cap must be rated X7R and sized for the inrush current during Flash programming (approximately 50 mA peak).
The 44-QFN (ML) exposed thermal pad (pin 45 / EP) MUST be soldered to a ground pour of at least 25 mm² to keep junction temperature within the -40 to +85 C industrial range. Estimated: at 40 MHz with all peripherals active, power dissipation is roughly 80 mW (5 V x 16 mA); with the exposed pad soldered, theta_JA is around 28 C/W giving a 2-3 C rise above ambient. Without the pad soldered, theta_JA exceeds 60 C/W and the part will derate badly in enclosed housings.
Route the ICSP clock (RB6/PGC) and data (RB7/PGD) lines with short, parallel traces and avoid routing them over switching signals to keep programming/debug reliable. Place the 4.7 kohm I2C pull-ups close to the PIC18F4525-I/ML if MSSP is used in I2C mode; weak pull-ups cause intermittent NACKs at 400 kHz Fast Mode. The MCLR pin (pin 1) requires a 10 kohm pull-up to VDD plus a 0.1 µF cap to ground for brown-out reset noise immunity - omitting this is a common cause of spurious resets in industrial environments.
Do not enable the 4x PLL (HSPLL mode) unless the crystal is rated for the resulting 40 MHz - many 10 MHz crystals cannot sustain PLL multiplication. Always configure the configuration bits (CONFIG1H) for the correct oscillator mode before first programming; an invalid setting can lock the device, requiring LVP recovery. Estimated: read-cycle time at 5 V / 40 MHz is 100 ns, so peripherals using internal oscillators (Timer1 with 32 kHz crystal) must use the lowest prescaler that still keeps the timer interrupt rate under 100 kHz to avoid CPU overload.
When driving long cables from the EUSART (RC6/RC7), add a 100 ohm source-series resistor to damp reflections; the PIC18F4525-I/ML has strong push-pull drivers capable of producing overshoot on cables longer than ~50 cm. For SPI buses exceeding 10 MHz on the MSSP, keep the SCK trace length-matched to SDI/SDO within 5 mm to prevent setup/hold violations on slave devices. The ADC inputs (RA0-RA5, RE0-RE2, AN8-AN9) sample best when the source impedance is below 2.5 kohm; above that, add an external buffer such as the MCP6001 op-amp.
Informações de conformidade
RoHS compliant per Microchip product page; lead-free finish. Not AEC-Q100 qualified - for automotive safety applications, use the PIC18F45K22-I/ML (AEC-Q100 Grade 1) in the same 44-QFN package.
