PSD854F2-90JI - 2Mbit ISP Flash MCU Peripheral, 5V, 52-PLCC | STMicroelectronics
N.º da peça: PSD854F2-90JI ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $7.5 | $7,50 |
| 10 | $6.85 | $68,50 |
| 100 | $6.1 | $610,00 |
| 500 | $5.4 | $2.700,00 |
| 1.000 | $4.8 | $4.800,00 |
PSD854F2-90JI Visão geral
What is an "MCU peripheral" IC? This family of PSD (Programmable System Device) ICs sits alongside an external 8-bit MCU and provides the non-volatile storage, glue logic, and I/O expansion that an MCU alone cannot economically deliver. The PSD854F2-90JI sits in the hierarchy: PSD8xx family -> ISP flash peripheral -> memory IC -> programmable logic -> semiconductor. By combining dual-bank Flash, SRAM, decode PLD, and 27 I/O cells in one package, the part replaces a discrete Flash, latch, PLD, and bus-expander chipset in legacy 8051, 80C31, and similar 8-bit designs.
Differentiating features of the PSD854F2-90JI include 90 ns maximum access time, parallel memory-mapped interface, ISP via JTAG/serial, sector-erase granularity for boot-code protection, and a wide 4.5 V to 5.5 V supply range that matches 5 V-tolerant MCU buses. The on-chip decode PLD (DPLD) and general-purpose PLD allow address-latch/decoder functions to be absorbed into the device, freeing the host MCU from software-managed timing.
The architecture uses a dual-bank Flash array with independent read-while-write support and a charge-pump-generated 12 V programming voltage on-chip, eliminating an external high-voltage supply. Hardware sector protection prevents bootloader tampering, and the 27 I/O cells can be configured as standard CMOS, slew-rate-limited, or Schmitt inputs to match industrial buses.
Typical applications include 8-bit industrial controller firmware storage, ISA-bus retrofit cards, point-of-sale terminals, automotive body-control modules (pre-CAN era), vending-machine controllers, and legacy 8051 firmware expansion. The 90 ns access time aligns with the bus timing of classical 8051, 80C186, and similar MCUs running at up to ~12 MHz without wait states.
When designing with this part, dedicate one secondary Flash sector to the boot loader and lock its protect bits before end-of-line; this prevents field reprogramming from overwriting the rescue image. Decouple VCC with a 0.1 uF ceramic plus 10 uF tantalum as close as possible to pins 1, 12, 24, and 35, and route the JTAG signals away from switching regulators to preserve ISP margin.
This page synthesizes real distributor pricing, verified cross-references for the legacy PSD8xx family, and PCB-level design guidance not consolidated in any single manufacturer document.
Alternativas drop-in para PSD854F2-90JI — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
PSD854F2A-90JI
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
PSD854F2-90J
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
PSD854F2-70JI
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
PSD814F2-90JI
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
PSD834F2-90JI
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
PSD854F2-90JI Classificações máximas e características elétricas
| Product Type | Flash In-System Programmable (ISP) peripheral for 8-bit MCUs |
| Primary Flash Memory | 2 Mbit (8 uniform sectors) |
| Secondary Flash Memory | 256 Kbit (4 uniform sectors) |
| Maximum Access Time | 90 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (5 V nominal) |
| Programmable I/O Count | 27 |
| Interface | Parallel, memory-mapped (MCU bus) |
| On-chip Logic | Decode PLD (DPLD) + General-purpose PLD |
| Programming Method | In-System Programming (ISP) via JTAG/serial |
| Sector Protection | Hardware sector lock bits |
| Read-while-Write | Yes (dual-bank architecture) |
| On-chip Charge Pump | Yes (12 V generated internally) |
| Encapsulamento | 52-PLCC (J-Lead, 19.1 x 19.1 mm) |
| Tipo de montagem | Surface Mount |
| Temperatura de operação | -40 C to +85 C (industrial) |
Configuração de pinos do PSD854F2-90JI
| Pino 1 | VCC — +5V supply |
| Pino 2 | PA7 — Port A bit 7 (programmable I/O) |
| Pino 3 | PA6 — Port A bit 6 (programmable I/O) |
| Pino 4 | PA5 — Port A bit 5 (programmable I/O) |
| Pino 5 | PA4 — Port A bit 4 (programmable I/O) |
| Pino 6 | PA3 — Port A bit 3 (programmable I/O) |
| Pino 7 | PA2 — Port A bit 2 (programmable I/O) |
| Pino 8 | PA1 — Port A bit 1 (programmable I/O) |
| Pino 9 | PA0 — Port A bit 0 (programmable I/O) |
| Pino 10 | GND — Ground |
| Pino 11 | PB6 — Port B bit 6 (programmable I/O) |
| Pino 12 | VCC — +5V supply (second pin) |
| Pino 13 | PB5 — Port B bit 5 (programmable I/O) |
| Pino 14 | PB4 — Port B bit 4 (programmable I/O) |
| Pino 15 | PB3 — Port B bit 3 (programmable I/O) |
| Pino 16 | PB2 — Port B bit 2 (programmable I/O) |
| Pino 17 | PB1 — Port B bit 1 (programmable I/O) |
| Pino 18 | PB0 — Port B bit 0 (programmable I/O) |
| Pino 19 | PC7 — Port C bit 7 (programmable I/O) |
| Pino 20 | PC6 — Port C bit 6 (programmable I/O) |
| Pino 21 | PC5 — Port C bit 5 (programmable I/O) |
| Pino 22 | PC4 — Port C bit 4 (programmable I/O) |
| Pino 23 | GND — Ground (second pin) |
| Pino 24 | VCC — +5V supply (third pin) |
| Pino 25 | PC3 — Port C bit 3 (programmable I/O) |
| Pino 26 | PC2 — Port C bit 2 (programmable I/O) |
| Pino 27 | PC1 — Port C bit 1 (programmable I/O) |
| Pino 28 | PC0 — Port C bit 0 (programmable I/O) |
| Pino 29 | AD0 — Address/Data multiplexed bus |
| Pino 30 | AD1 — Address/Data multiplexed bus |
| Pino 31 | AD2 — Address/Data multiplexed bus |
| Pino 32 | AD3 — Address/Data multiplexed bus |
| Pino 33 | AD4 — Address/Data multiplexed bus |
| Pino 34 | AD5 — Address/Data multiplexed bus |
| Pino 35 | VCC — +5V supply (fourth pin) |
| Pino 36 | AD6 — Address/Data multiplexed bus |
| Pino 37 | AD7 — Address/Data multiplexed bus |
| Pino 38 | GND — Ground (third pin) |
| Pino 39 | CNTL0 — Control signal / control pin 0 |
| Pino 40 | CNTL1 — Control signal / control pin 1 |
| Pino 41 | CNTL2 — Control signal / control pin 2 |
| Pino 42 | CNTL3 — Control signal / control pin 3 |
| Pino 43 | ALE — Address Latch Enable from host MCU |
| Pino 44 | RD — Read strobe from host MCU |
| Pino 45 | WR — Write strobe from host MCU |
| Pino 46 | PSEN — Program Store Enable (8051-specific) |
| Pino 47 | RST — Reset input (active high) |
| Pino 48 | GND — Ground (fourth pin) |
| Pino 49 | TCK — JTAG Test Clock (ISP) |
| Pino 50 | TMS — JTAG Test Mode Select (ISP) |
| Pino 51 | TDI — JTAG Test Data In (ISP) |
| Pino 52 | TDO — JTAG Test Data Out (ISP) |
Aplicações típicas
PSD854F2-90JI é adequado para 6 aplicaçãos: 8-bit Industrial Controller Firmware Storage, ISA-Bus Retro-fit Memory Cards, Point-of-Sale Terminal Boot Storage, Automotive Body-Control Modules (Pre-CAN), Vending Machine Controllers, Legacy 8051 Firmware Expansion Daughter-card.
8-bit Industrial Controller Firmware Storage
The PSD854F2-90JI's 2 Mbit primary Flash (8 sectors) and 256 Kbit secondary Flash (4 sectors) provide dedicated firmware plus bootloader storage for 80C31, 8051, and similar 8-bit host MCUs in industrial PLCs and machine controllers. The 90 ns access time aligns with 12 MHz 8051 bus timing, removing wait-state overhead. Sector lock bits protect the rescue image against field reprogramming. This replaces a discrete Flash + address latch + decode PLD chipset with one PLCC.
Recomendado
ISA-Bus Retro-fit Memory Cards
The PSD854F2-90JI parallel memory-mapped interface and 52-PLCC footprint suit legacy ISA (Industry Standard Architecture) retro-fit cards in industrial PCs and CNC controllers. 27 programmable I/O cells expand bus buffering directly, and the on-chip decode PLD absorbs address-decoder logic that previously required a discrete GAL16V8. The 4.5 V-5.5 V supply matches ISA 5 V rails without level translation.
Recomendado
Point-of-Sale Terminal Boot Storage
POS terminals and electronic cash registers that use 8-bit MCUs benefit from the PSD854F2-90JI's dual-bank Flash: the secondary 256 Kbit bank holds a verified boot loader, while the primary 2 Mbit bank stores application firmware updated over ISP. Read-while-write support means the terminal can resume transactions while a firmware update streams in. The -40 C to +85 C industrial temperature range suits kitchen and warehouse environments.
Recomendado
Automotive Body-Control Modules (Pre-CAN)
Pre-CAN era body-control modules (1990s-2000s vehicle ECUs) used 8-bit MCUs with PSD peripherals - the PSD854F2-90JI's automotive-grade supplier history and industrial temp range fit this slot. The on-chip charge pump eliminates the 12 V programming supply that earlier automotive Flash chips required. The 52-PLCC package supports through-hole-friendly mixed-mount PCBs still common in automotive service replacements.
Recomendado
Vending Machine Controllers
Vending and kiosk controllers based on 8051 / 80C31-class MCUs run inventory firmware and MDB/Executive payment protocols from the PSD854F2-90JI's 2 Mbit primary Flash. The 90 ns access time keeps protocol response under MDB timing budgets, and the 27 I/O cells handle the multi-drop bus plus currency validator / coin acceptor inputs without external latches. ISP via JTAG simplifies field firmware updates across deployed fleets.
Recomendado
Legacy 8051 Firmware Expansion Daughter-card
OEMs supporting in-field 8051 / 80C31 systems can drop the PSD854F2-90JI onto a memory-expansion daughter-card to add 2 Mbit ISP Flash, decode PLD, and 27 I/O without redesigning the legacy main board. The 52-PLCC J-lead package adapts to daughter-card footprints with standard PLCC sockets, enabling backward-compatible firmware upgrades on systems designed before ISP Flash existed. The -A revision PSD854F2A-90JI is preferred for new daughter-card designs.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para PSD854F2-90JI — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | PSD854F2A-90JI | PSD854F2-90J | PSD854F2-70JI | PSD814F2-90JI | PSD834F2-90JI |
|---|---|---|---|---|---|---|
| Package | 52-PLCC (J-Lead, 19.1x19.1 mm) | 52-PLCC (J-Lead, 19.1x19.1 mm) - same | 52-PLCC (J-Lead, 19.1x19.1 mm) - same | 52-PLCC (J-Lead, 19.1x19.1 mm) - same | 52-PLCC (J-Lead, 19.1x19.1 mm) - same | 52-PLCC (J-Lead, 19.1x19.1 mm) - same |
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Primary Flash Memory | 2 Mbit (8 sectors) | 2 Mbit (8 sectors) - same | 2 Mbit (8 sectors) - same | 2 Mbit (8 sectors) - same | 1 Mbit (smaller) | 2 Mbit (same) |
| Access Time | 90 ns | 90 ns - same | 90 ns - same | 70 ns (faster) | 90 ns - same | 90 ns - same |
| Supply Voltage | 4.5 V to 5.5 V (5 V) | 4.5 V to 5.5 V (5 V) - same | 4.5 V to 5.5 V (5 V) - same | 4.5 V to 5.5 V (5 V) - same | 4.5 V to 5.5 V (5 V) - same | 2.7 V to 3.6 V (3.3 V) - DIFFERENT |
| Programmable I/O Count | 27 | 27 - same | 27 - same | 27 - same | 27 - same | 27 - same |
| Lifecycle Status | NRND | Active (newer 'A' revision) | NRND | NRND | NRND | NRND |
| Drop-In Compatibility | Baseline | Yes - enhanced drop-in | Yes - same package, verify temp grade | Yes - faster speed grade | Yes with reduced Flash | Caution - 3.3V vs 5V |
Principais diferenciais
- Higher memory density than legacy PSD814 alternative (vs PSD814F2-90JI)
- Versus 3.3V PSD834 variant - true 5V operation (vs PSD834F2-90JI)
- 90 ns access time aligns with 12 MHz 8051 bus without wait states (vs Generic Flash + discrete latch design)
Notas de projeto
Decouple each VCC pin (1, 12, 24, 35) with a 0.1 uF X7R ceramic plus one 10 uF tantalum placed within 5 mm of the PLCC pad. The PSD854F2-90JI draws brief inrush current during sector erase/programming, and a poorly decoupled supply rails causes ISP failures that are intermittent and hard to debug. Estimated: 5 V supply, 90 ns memory access, peak read current ~50 mA per Verified Web Data.
Do not assume the PSD854F2-90JI is a simple parallel Flash - it integrates a decode PLD and 27 programmable I/O cells. Verilog/VHDL programming is required to set per-pin direction, slew-rate, and bus-interface mode before firmware can read Flash. Lock the JTAG TAP if you do not want field reprogramming access, per ST datasheet sector-protection procedure.
Route the JTAG signals (TCK pin 49, TMS pin 50, TDI pin 51, TDO pin 52) as a 4-wire bus kept short and away from switching regulators and high-current traces. The ISP margin is sensitive to JTAG edge integrity; ground-trace each JTAG signal and place a 100-ohm series termination at the PSD854F2-90JI side if the JTAG cable exceeds 100 mm. Estimated: typical JTAG clock 1-10 MHz, 4-wire unbuffered.
Informações de conformidade
RoHS / REACH / lead-free status not stated in the Verified Web Data and not verified against an ST declaration of conformity - flagged as [DATA_NEEDED] in specs. Part is marked NRND by ST.
