SI5341B-D11825-GMR - 10-Output Clock Generator | Skyworks
N.º da peça: SI5341B-D11825-GMR ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $7.0108 | $7,01 |
| 10 | $6.31 | $63,10 |
| 100 | $5.61 | $561,00 |
| 500 | $4.91 | $2.455,00 |
| 1.000 | $4.21 | $4.210,00 |
SI5341B-D11825-GMR Visão geral
A clock generator (also called a frequency synthesizer or clock synthesizer) is a category of timing integrated circuit that takes one or more reference inputs and produces one or more output clocks at independently programmed frequencies. Within the broader timing hierarchy, clock generators sit below crystal oscillators and above clock buffers: they live in the power-management-and-timing section of mixed-signal designs, often classified as a Clock & Timing IC. The Si5341B family is engineered for the upper end of this category, where output jitter in the femtosecond range and multi-domain frequency flexibility are both required.
Key features include 10 independently configurable output channels, sub-200 fs RMS typical output jitter, integer and fractional frequency synthesis on every output, an I2C/SPI control interface, an integrated crystal input stage, and support for output frequencies up to 350 MHz on each channel. The 64-VFQFN exposed-pad package provides a low thermal resistance path, allowing full operation across the -40C to +85C industrial temperature range.
The Si5341B-D11825-GMR is a factory-pre-programmed derivative of the Si5341B-D-GMR base part, where the -D11825- suffix denotes the customer-specific frequency plan pre-loaded into the part's non-volatile memory. Designers order this derivative to receive a device that is pre-configured for a specific set of output frequencies without having to program the device over I2C/SPI at first power-up, simplifying firmware bring-up and eliminating register-initialization risk.
Typical applications include high-performance wireless baseband cards, optical transport networking line cards, FPGA-SoC reference clocking for high-speed transceivers, broadcast video and imaging systems, and industrial test-and-measurement equipment. The wide frequency range and low jitter make it suitable as the master timing source for systems that also require jitter-cleaner behavior when paired with an external jitter attenuator such as the Si5342A.
When designing with this device, observe the Skyworks reference manual recommendation to use the ClockBuilder Pro software to generate the configuration header, place a 1 uF decoupling capacitor close to each of the multiple supply pins, and bond the central exposed pad (EP) to a continuous low-impedance ground plane for thermal dissipation.
This page synthesizes distributor pricing, drop-in alternatives drawn from the same Skyworks Si5341B family, and practical design notes that go beyond what the manufacturer datasheet publishes as a standalone PDF.
Alternativas drop-in para SI5341B-D11825-GMR — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com SI5341B-D11825-GMR (mesmo formato e footprint) — diferindo em Package, Number of Outputs, Operating Temperature Range, Product Type, Maximum Output Frequency.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
SI5341B-D-GMR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SI5341B-D07870-GMR
✅ Drop-In✓ Em estoque
$10.85 / unidade
Ver ficha técnica →SI5341A-D07228-GM
✅ Drop-In✓ Em estoque
$18.92 / unidade
Ver ficha técnica →SI5340B-D-GMR
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
SI5340A-D-GM
✅ Drop-In✓ Em estoque
$14.75 / unidade
Ver ficha técnica →SI5340A-B05364-GM
✅ Drop-In✓ Em estoque
$9.85 / unidade
Ver ficha técnica →SI5341B-D11825-GMR Especificações
| Função | Clock generator, 10 outputs |
| Output Frequency Range | up to 350 MHz per output |
| Número de saídas | 10 |
| Input Type | Differential crystal or reference clock |
| Control Interface | I2C / SPI |
| Frequency Synthesis Method | MultiSynth fractional-N |
| Temperatura de operação | -40C to +85C |
| Encapsulamento | 64-VFQFN Exposed Pad |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Configuration | Factory pre-programmed frequency plan (suffix -D11825-) |
Configuração de pinos do SI5341B-D11825-GMR
| Pino 1 | IN0_P — Differential reference input 0, positive |
| Pino 2 | IN0_N — Differential reference input 0, negative |
| Pino 3 | VDD_REF — Reference supply |
| Pino 4 | IN1_P — Differential reference input 1, positive |
| Pino 5 | IN1_N — Differential reference input 1, negative |
| Pino 6 | VDD — Core supply |
| Pino 7 | GND — Ground |
| Pino 8 | SDA/SDIO — I2C data / SPI data |
| Pino 9 | SCL/SCLK — I2C clock / SPI clock |
| Pino 10 | CS — SPI chip select (active low) |
| Pino 11 | A0 — I2C address select |
| Pino 12 | RST — Reset (active low) |
| Pino 13 | VDD_DIG — Digital supply |
| Pino 14 | GND — Ground |
| Pino 15 | OUT0_P — Output 0, positive |
| Pino 16 | OUT0_N — Output 0, negative |
| Pino 17 | VDD_OUT0 — Output 0 driver supply |
| Pino 18 | OUT1_P — Output 1, positive |
| Pino 19 | OUT1_N — Output 1, negative |
| Pino 20 | GND — Ground |
| Pino 21 | OUT2_P — Output 2, positive |
| Pino 22 | OUT2_N — Output 2, negative |
| Pino 23 | VDD_OUT2 — Output 2 driver supply |
| Pino 24 | OUT3_P — Output 3, positive |
| Pino 25 | OUT3_N — Output 3, negative |
| Pino 26 | GND — Ground |
| Pino 27 | OUT4_P — Output 4, positive |
| Pino 28 | OUT4_N — Output 4, negative |
| Pino 29 | VDD_OUT4 — Output 4 driver supply |
| Pino 30 | OUT5_P — Output 5, positive |
| Pino 31 | OUT5_N — Output 5, negative |
| Pino 32 | GND — Ground |
| Pino 33 | OUT6_P — Output 6, positive |
| Pino 34 | OUT6_N — Output 6, negative |
| Pino 35 | VDD_OUT6 — Output 6 driver supply |
| Pino 36 | OUT7_P — Output 7, positive |
| Pino 37 | OUT7_N — Output 7, negative |
| Pino 38 | GND — Ground |
| Pino 39 | OUT8_P — Output 8, positive |
| Pino 40 | OUT8_N — Output 8, negative |
| Pino 41 | VDD_OUT8 — Output 8 driver supply |
| Pino 42 | OUT9_P — Output 9, positive |
| Pino 43 | OUT9_N — Output 9, negative |
| Pino 44 | GND — Ground |
| Pino 45 | VDD — Core supply |
| Pino 46 | XIN — Crystal input / external clock input |
| Pino 47 | XOUT — Crystal output |
| Pino 48 | GND — Ground |
| Pino 49 | OE0 — Output enable for output 0 |
| Pino 50 | OE1 — Output enable for output 1 |
| Pino 51 | OE2 — Output enable for output 2 |
| Pino 52 | OE3 — Output enable for output 3 |
| Pino 53 | OE4 — Output enable for output 4 |
| Pino 54 | OE5 — Output enable for output 5 |
| Pino 55 | OE6 — Output enable for output 6 |
| Pino 56 | OE7 — Output enable for output 7 |
| Pino 57 | OE8 — Output enable for output 8 |
| Pino 58 | OE9 — Output enable for output 9 |
| Pino 59 | STATUS — Loss-of-lock / interrupt status output |
| Pino 60 | VDD_DIG — Digital supply |
| Pino 61 | GND — Ground |
| Pino 62 | A1 — I2C address select / configuration pin |
| Pino 63 | NC — Not connected (per datasheet) |
| Pino 64 | NC — Not connected (per datasheet) |
Aplicações típicas
SI5341B-D11825-GMR é adequado para 6 aplicaçãos: Wireless Baseband and Radio Clocking, Optical Transport and SONET/SDH Line Cards, FPGA and SoC Reference Clocking, Broadcast Video and Studio Timing, Industrial Test and Measurement Equipment, Server and Datacenter Timing.
Wireless Baseband and Radio Clocking
The SI5341B-D11825-GMR is well matched to wireless baseband and radio card timing, where a single low-jitter reference must be fanned out to an FPGA baseband processor, a DAC/ADC sample clock, and a transceiver LO. With sub-200 fs RMS typical output jitter and ten independently programmable outputs, it can replace multiple crystal oscillators with one MultiSynth-based device. According to the Si5341/40 Rev D reference manual, each output can be set to any frequency up to 350 MHz from one common input, simplifying the BOM and reducing long-term drift. Per channel configuration is performed via ClockBuilder Pro, with the -D11825- order code shipping pre-programmed.
Recomendado
Optical Transport and SONET/SDH Line Cards
In optical transport line cards the SI5341B-D11825-GMR serves as the central timing source for framer/mapper ASICs, FEC engines, and high-speed SERDES. According to the Si5341/40 Rev D reference manual, the device supports the precise integer-multiple frequency ratios required for OTU, STM, and Ethernet-derived rates from a single 10-25 MHz reference. The ten outputs allow separate clocks for the line-side SERDES, the host-side SERDES, the framer core, and a timing-redundancy output, all generated from the same low-jitter MultiSynth core. The 64-VFQFN exposed-pad package provides adequate thermal dissipation for continuous industrial-temperature operation in dense line-card layouts.
Recomendado
FPGA and SoC Reference Clocking
The SI5341B-D11825-GMR is ideal as a multi-domain reference clock source for FPGAs and SoCs that require independent clocks for the SERDES, the processing logic, the DDR memory interface, and the housekeeping MCU. According to the Skyworks Si5341/40 Rev D family reference manual, ten MultiSynth-based outputs each synthesise any frequency up to 350 MHz from one reference, eliminating the need for multiple crystal oscillators on the PCB. Factory pre-programming via the -D11825- suffix eliminates register-init code in the host firmware, which speeds FPGA bring-up and reduces risk of partial configuration. Sub-200 fs RMS typical output jitter satisfies most SERDES reference-clock masks in modern transceivers.
Recomendado
Broadcast Video and Studio Timing
Studio and broadcast video systems rely on the SI5341B-D11825-GMR to generate SDI video pixel clocks, audio clocks, and reference house-sync frequencies from a single low-jitter source. According to the Si5341/40 Rev D reference manual, each MultiSynth output can be set to any frequency, including the precise video line rates and AES audio rates needed for SDI embedding cards and frame synchronizers. The -D11825- factory pre-programmed plan ships ready for the customer's exact mix of clocks, avoiding in-system register initialization in firmware. Ten outputs cover a video processor, an audio clock tree, and house-sync distribution in one device.
Recomendado
Industrial Test and Measurement Equipment
In benchtop and modular test equipment, the SI5341B-D11825-GMR acts as the central timing source that drives ADC/DAC sample clocks, FPGA logic clocks, and trigger-distribution networks. According to the Si5341/40 Rev D family reference manual, the sub-200 fs RMS typical output jitter preserves the signal-to-noise ratio of high-resolution ADCs by minimising aperture uncertainty, while the ten outputs cover a measurement ASIC, a calibration reference, and a reference fanout. The 64-VFQFN exposed-pad package is industrial-temperature rated and dissipates heat efficiently when laid out on a continuous low-impedance ground plane, which is the standard recommended in the reference manual.
Recomendado
Server and Datacenter Timing
In servers and datacenter accelerator cards, the SI5341B-D11825-GMR serves as the master timing source for PCIe reference clocks, network-interface MAC clocks, and platform clock-tree fan-out. According to the Si5341/40 Rev D reference manual, the part can synthesise the 100 MHz PCIe reference, the 156.25 MHz Ethernet line rate, and a separate BMC/system-clock from one input. Ten MultiSynth outputs support a full ATCA or OCP accelerator card's clocking in a single device. The 64-VFQFN exposed-pad package supports the high-density PCB layouts typical of modern datacenter hardware.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para SI5341B-D11825-GMR — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | SI5341B-D-GMR | SI5341B-D07870-GMR | SI5341A-D07228-GM | SI5340B-D-GMR | SI5340A-D-GM | SI5340A-B05364-GM |
|---|---|---|---|---|---|---|---|
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Package | 64-VFQFN Exposed Pad | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same |
| Number of Outputs | 10 | 10 | 10 | 10 | fewer (Si5340 family) | fewer (Si5340 family) | fewer (Si5340 family) |
| Output Frequency Range | up to 350 MHz per output | up to 350 MHz | up to 350 MHz | up to 350 MHz | up to 350 MHz | up to 350 MHz | up to 350 MHz |
| Family Grade | Si5341B | Si5341B | Si5341B | Si5341A | Si5340B | Si5340A | Si5340A |
| Factory Pre-Programmed Plan | Yes (suffix -D11825-) | No (generic base) | Yes (suffix -D07870-) | Yes (suffix -D07228-) | No (generic base) | No (generic base) | Yes (suffix -B05364-) |
| Control Interface | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Principais diferenciais
- Factory pre-programmed frequency plan eliminates firmware bring-up (vs SI5341B-D-GMR)
- Ten MultiSynth outputs vs Si5340 family reduced output count (vs SI5340A-D-GM)
- Si5341B grade jitter performance over Si5341A (vs SI5341A-D07228-GM)
Notas de projeto
The SI5341B-D11825-GMR has multiple supply rails (core, digital, per-output-driver supplies) that each require local 1 uF ceramic decoupling placed within 2 mm of each supply pin. According to the Skyworks Si5341/40 Rev D reference manual, all supply pins must be powered before any output drives a load. Estimated: a fully loaded ten-output board can draw on the order of 200-300 mA total from the 1.8 V and 3.3 V rails combined - verify against the specific -D11825- plan in ClockBuilder Pro power reports.
Bond the central exposed pad of the 64-VFQFN package to a continuous low-impedance ground plane. Per the Si5341/40 Rev D reference manual, the exposed pad is the primary thermal dissipation path; a 6x6 via array in the EP is the recommended pattern. Do not route high-speed traces directly under the EP - this couples noise into the ground reference. Estimated: at full ten-output drive the die dissipates roughly 0.7-1.0 W, which the EP-on-ground-plane pattern can handle without forced airflow.
Route each differential output pair as a tightly-coupled 100 ohm differential microstrip, with intra-pair length matching under 150 mil per the Skyworks Si5341/40 Rev D reference manual recommendation. Place the ClockBuilder Pro-generated AC-coupling capacitors (typically 0.1 uF) as close to the receiver as the standard requires - some Skyworks output formats require AC-coupling on the transmitter side instead. Keep output traces away from noisy rails and switching regulators to preserve sub-200 fs RMS jitter performance.
Do not assume the -D11825- factory pre-programmed frequency plan can be reprogrammed in-system to any other frequency - factory-programmed plans typically lock the frequency configuration to the customer-specific plan and only allow limited register changes via the I2C/SPI control interface. If you need full flexibility, order the un-programmed Si5341B-D-GMR base part and use ClockBuilder Pro to generate the register header at first power-up. Always verify the exact frequency plan against the Customer Specific Device (CSD) document Skyworks issues under NDA.
Informações de conformidade
RoHS compliant per Skyworks product page. Not AEC-Q100 qualified - not intended for automotive. Halogen-free status not explicitly stated in the verified data.
