SN74LV123ARGYR - Dual Retriggerable Mono Multivibrator | TI
N.º da peça: SN74LV123ARGYR ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $0.96 | $0,96 |
| 10 | $0.86 | $8,60 |
| 100 | $0.62 | $62,00 |
| 500 | $0.48 | $240,00 |
| 1.000 | $0.39 | $390,00 |
SN74LV123ARGYR Visão geral
A monostable multivibrator, also called a one-shot, is a sequential logic element with one stable state and one quasi-stable state. When triggered, the output transitions to the active state for a precisely defined interval then returns to the idle state, regardless of further trigger activity until the timing capacitor discharges. Retriggerable one-shots extend the output pulse if a new trigger arrives during the timing window, allowing pulse-width extension under software or hardware control. The 'LV123A family belongs to TI's LV-A logic series, optimized for low-voltage, low-power mixed-signal designs and ideally suited for battery-powered or interface-isolation tasks.
Key features include Schmitt-trigger inputs that provide hysteresis for slow or noisy edges, complementary Q and /Q outputs per channel, an internal clear input to abort timing, and a typical VOLP/VOHV output bounce/undershoot below 1 V at 25 °C. The wide 2 V to 5.5 V supply range enables direct interface to 3.3 V and 5 V logic without level translators, and the wide operating temperature range of -40 °C to +125 °C supports industrial and automotive-grade designs.
Internally the device uses CMOS logic with TTL-compatible input thresholds, achieving typical ICC quiescent current low enough for portable designs. Each channel shares a common VCC and GND but has independent timing components (R_ext and C_ext), enabling two simultaneous one-shot functions in a single IC footprint.
Typical applications include debounce circuits for mechanical switches, watchdog timers for microcontrollers, missing-pulse detectors in safety and instrumentation, pulse-width modulation control loops, and waveform generation for digital logic testers. Designers also use the SN74LV123A in line-card timing, sequencing for multi-rail power systems, and as a fixed-delay element in digital communication front-ends.
When designing with this device, select the timing resistor within the recommended range and use a low-leakage timing capacitor (NP0/C0G or film) to preserve pulse-width accuracy. Place timing components close to the R_ext/C_ext pins to minimize parasitic capacitance that would otherwise extend the pulse and degrade retrigger integrity.
This page consolidates distributor pricing, verified drop-in same-package alternatives, and PCB layout guidance that goes beyond the manufacturer datasheet, helping procurement and design engineers select and qualify this part faster.
Alternativas drop-in para SN74LV123ARGYR — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
SN74LV123ARGYRG4
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SN74LV123APWR
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
SN74LV123APW
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
SN74LV123ARGYR Classificações máximas e características elétricas
| Função | Dual retriggerable monostable multivibrator (one-shot) |
| Number of Channels | 2 |
| Logic Family | 74LV |
| Supply Voltage (VCC) | 2 V to 5.5 V |
| Propagation Delay (tpd) | 13 ns (max, per DigiKey); 8.3 ns (typical) |
| Output Drive Current | 12 mA |
| Trigger Type | Falling-edge with Schmitt-trigger input |
| Input Hysteresis | Schmitt-trigger inputs (per datasheet) |
| Outputs per Channel | Q and complementary /Q |
| Clear Input | Yes (active-low, common to both channels) |
| Pulse Width Range | Set by external R_ext and C_ext (see datasheet) |
| Temperatura de operação | -40 °C to +125 °C |
| Encapsulamento | 16-pin VQFN (RGY), 4 mm x 3.5 mm |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Lead-Free | Yes |
Configuração de pinos do SN74LV123ARGYR
| Pino 1 | 1R_EXT — Channel 1 timing resistor connection |
| Pino 2 | 1C_EXT — Channel 1 timing capacitor connection |
| Pino 3 | 1CLR — Channel 1 clear input (active-low) |
| Pino 4 | 1A — Channel 1 trigger A input |
| Pino 5 | 1B — Channel 1 trigger B input |
| Pino 6 | 1Q — Channel 1 non-inverted output |
| Pino 7 | 1Q_bar — Channel 1 inverted output |
| Pino 8 | GND — Ground |
| Pino 9 | 2Q_bar — Channel 2 inverted output |
| Pino 10 | 2Q — Channel 2 non-inverted output |
| Pino 11 | 2B — Channel 2 trigger B input |
| Pino 12 | 2A — Channel 2 trigger A input |
| Pino 13 | 2CLR — Channel 2 clear input (active-low) |
| Pino 14 | 2C_EXT — Channel 2 timing capacitor connection |
| Pino 15 | 2R_EXT — Channel 2 timing resistor connection |
| Pino 16 | VCC — Supply voltage (2 V to 5.5 V) |
Aplicações típicas
SN74LV123ARGYR é adequado para 7 aplicaçãos: Mechanical Switch Debounce, Watchdog Timer for MCU Reset, Missing-Pulse Detector, Pulse-Width Modulation Generator, Digital Sequence Timing, Line-Card Timing in Telecom, Waveform Generator for Logic Analyzers.
Mechanical Switch Debounce
The SN74LV123ARGYR's Schmitt-trigger inputs reject the slow, noisy edges produced by mechanical switches and tactile buttons. A single channel stretches a multi-millisecond bounce event into a clean, single digital pulse, with pulse width set by an external R_ext (typically 10 kΩ to 1 MΩ) and C_ext (10 nF to 10 µF) network. The retriggerable architecture prevents missed presses even if the switch settles during the timing window, while the /Q complementary output enables edge-to-level conversion without additional inverters.
Recomendado
Watchdog Timer for MCU Reset
The SN74LV123ARGYR functions as a watchdog reset generator: a periodic heartbeat pulse from the MCU retriggers channel 1, and a missing pulse causes the Q output to time out and assert /RESET. With VCC from 2 V to 5.5 V the device directly drives microcontroller reset pins on 3.3 V and 5 V MCUs without level shifting. The 8.3 ns propagation delay and 12 mA output drive handle most CMOS reset busses, while the Schmitt-trigger input rejects noise on long board-trace heartbeats.
Recomendado
Missing-Pulse Detector
In safety and instrumentation systems, channel 2 of the SN74LV123ARGYR can be configured as a missing-pulse detector. A periodic trigger pulse from a sensor retriggers the timer; if a pulse is absent beyond the RC-defined window, the /Q output asserts a fault flag. With operating temperature -40 °C to +125 °C the device functions in industrial process-control environments, and the 2 V to 5.5 V supply range supports battery-backed 3.3 V monitoring rails.
Recomendado
Pulse-Width Modulation Generator
The SN74LV123ARGYR can drive a simple PWM control loop by retriggering a fixed-pulse one-shot and combining with a variable-frequency clock on the second channel. The complementary Q and /Q outputs feed a half-bridge gate driver, with the VQFN-16 package's 4 mm x 3.5 mm footprint fitting dense power-conversion PCBs. Designers must size R_ext/C_ext for the desired duty cycle and ensure pulse widths exceed the 8.3 ns propagation delay for clean switching edges.
Recomendado
Digital Sequence Timing
For multi-rail power-up sequencing, the SN74LV123ARGYR provides two independent fixed delays to stagger enable signals for FPGAs, ASICs, and analog blocks. The /Q output of channel 1 can trigger channel 2 through an RC network, creating cascaded delays with no additional glue logic. Operating from 2 V to 5.5 V and -40 °C to +125 °C, it qualifies for both consumer sequencing and industrial sequencing chains.
Recomendado
Line-Card Timing in Telecom
In telecom line cards, the SN74LV123ARGYR provides fixed-window pulse stretching for framing, ringing-cadence, and supervision timers. The 16-pin VQFN (RGY) package fits under shields with 4 mm x 3.5 mm outline, and the wide 2 V to 5.5 V supply supports legacy 5 V logic and newer 3.3 V DSP subsystems. The dual-channel architecture enables two timing functions per IC, reducing BOM count versus single one-shots.
Recomendado
Waveform Generator for Logic Analyzers
Test and measurement front-ends use the SN74LV123ARGYR to generate clean, repeatable pulse trains for logic-analyzer stimulus. With retrigger capability the device can extend a pulse into a controlled-width waveform that emulates asynchronous logic events. The 8.3 ns typical propagation delay and 12 mA drive support test fixtures below 50 MHz, with the 16-pin VQFN footprint fitting compact probe-board designs.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para SN74LV123ARGYR — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | SN74LV123ARGYRG4 | SN74LV123APWR | SN74LV123APW |
|---|---|---|---|---|
| Package | VQFN-16 (RGY) 4x3.5 mm | VQFN-16 (RGY) 4x3.5 mm - same | VQFN-16 (RGY) 4x3.5 mm - same | VQFN-16 (RGY) 4x3.5 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Supply Voltage (VCC) | 2 V to 5.5 V | 2 V to 5.5 V | 2 V to 5.5 V | 2 V to 5.5 V |
| Propagation Delay | 8.3 ns typical / 13 ns max | 8.3 ns typical / 13 ns max | 8.3 ns typical / 13 ns max | 8.3 ns typical / 13 ns max |
| Output Drive Current | 12 mA | 12 mA | 12 mA | 12 mA |
| Channels | 2 | 2 | 2 | 2 |
| Operating Temperature | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C |
| Lead-Free / RoHS | Yes / Compliant | Yes (G4 finish) / Compliant | Yes / Compliant | Yes / Compliant |
Principais diferenciais
- Same-die G4 finish revision available as drop-in (vs SN74LV123ARGYRG4)
- Industry-standard 74LV123 logic die (vs SN74LV123APWR)
- Wide 2 V to 5.5 V supply range (vs SN74LV123APW)
Notas de projeto
Place a 100 nF decoupling capacitor as close as possible to the VCC pin (pin 16) of the SN74LV123ARGYR, and add a bulk 1 µF to 10 µF capacitor near the IC on the VCC trace. Decoupling the supply prevents logic-level jitter during output transitions, especially when both channels fire simultaneously. Use a wide, low-inductance VCC/GND trace or polygon for the exposed paddle (which is electrically tied to GND internally on most RGY revisions) to minimize switching noise.
Route the R_EXT and C_EXT timing component traces as short and direct as possible to the IC pins. Long traces introduce parasitic capacitance that extends the output pulse beyond the calculated t = R × C duration. Place C_EXT close to the IC and tie its other terminal directly to GND. For sub-microsecond pulses, use an NPO/C0G ceramic capacitor instead of X7R to minimize voltage-coefficient drift of C_EXT.
Do not leave the CLR pin floating; tie it to VCC through a 10 kΩ pull-up if not driven actively, otherwise noise may prematurely abort the timing cycle. Avoid R_EXT values outside the datasheet's recommended range (typically 5 kΩ to 1 MΩ); values below 5 kΩ overstress the internal discharge transistor and shorten the device's lifetime. Trigger pulses must satisfy the minimum pulse-width specification in the datasheet (typically 50 ns), or retrigger logic may behave unpredictably.
Informações de conformidade
RoHS and REACH compliant per TI product page. Lead-free (Pb-free) finish. AEC-Q100 qualification status not explicitly stated; verify with TI for automotive applications.
